Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.

Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.

Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.

Abstract: Examples include techniques for determining validity of a memory used with a memory controller. Examples include a system having a memory device including a non-volatile memory and a memory controller, where the memory controller includes a validation component including a hash function and a hash table. In embodiments, the validation component performs, during a time of manufacturing of the memory controller, a test of the non-volatile memory to produce first test results, generates a first hash of the first test results using the hash function, and stores the first hash in the hash table. Later, the validation component performs, during a time of use of the memory controller after the time of manufacturing, the test of the non-volatile memory to produce second test results, generates a second hash of the second test results using the hash function, compares the first hash from the hash table with the second hash, and indicates an invalid memory when the first hash does not match the second hash.

Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.

Abstract: In one embodiment, an unpredictable nature of the storage properties in what is otherwise referred to as the “lockout period” following the programming of a non-volatile bitcell in a bitcell programming interval, is advantageously utilized in a random number generation mode to read random numbers from the memory. Accordingly, instead of locking out read operations in a lockout interval, a read operation may be performed in that or a similarly placed interval to read a bit state of the bitcell, which bit state is random in nature. The instability of the storage property varies from bitcell to bitcell and therefore may be used to generate a set of random bits from a block of bitcells. Other aspects are described herein.

Abstract: In one embodiment, an apparatus comprises: a challenger logic to issue a challenge to a responder logic, the challenge including an address of a portion of an array of a non-volatile memory; and the responder logic to receive the challenge and read data from the portion of the array at a read time less than a lockout period and at a demarcation voltage. The challenger logic may be configured to verify the challenge if the read data matches an expected read value, where the expected read value is determined based on configuration parameter information including compensation data associated with the portion of the array. Other embodiments are described and claimed.