Abstract: A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 ?m to about 2 ?m) P-type liner instead of completely filling the trench with P-type material. Inside the P-type liner, the trench may then be filled with a passive fill material. Filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. However, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.

Abstract: A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.

Abstract: A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.

Abstract: A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.

Abstract: A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.