Patents by Inventor Amirhasan Nourbakhsh
Amirhasan Nourbakhsh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830824Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.Type: GrantFiled: March 26, 2021Date of Patent: November 28, 2023Assignee: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
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Patent number: 11769665Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.Type: GrantFiled: January 11, 2022Date of Patent: September 26, 2023Assignee: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Raman Gaire, Tyler Sherwood, Lan Yu, Roger Quon, Siddarth Krishnan
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Publication number: 20230223256Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Applicant: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Raman Gaire, Tyler Sherwood, Lan Yu, Roger Quon, Siddarth Krishnan
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Patent number: 11508734Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: December 11, 2020Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Publication number: 20220310531Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
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Patent number: 11127745Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.Type: GrantFiled: June 19, 2020Date of Patent: September 21, 2021Assignee: Micron Technology, Inc.Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
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Publication number: 20210098463Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: December 11, 2020Publication date: April 1, 2021Applicant: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Patent number: 10886282Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 26, 2020Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Publication number: 20200321340Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
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Publication number: 20200235103Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 26, 2020Publication date: July 23, 2020Applicant: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Patent number: 10707212Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.Type: GrantFiled: December 28, 2018Date of Patent: July 7, 2020Assignee: Micron Technology, Inc.Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
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Publication number: 20200212046Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
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Publication number: 20200111796Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Applicant: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Patent number: 10615165Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: October 4, 2018Date of Patent: April 7, 2020Assignee: Micron Technology, Inc.Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
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Patent number: 9337273Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.Type: GrantFiled: March 29, 2013Date of Patent: May 10, 2016Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Amirhasan Nourbakhsh, Mirco Cantoro, Cedric Huyghebaert, Mark Heyns, Stefan DeGendt
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Patent number: 9293536Abstract: A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.Type: GrantFiled: December 16, 2014Date of Patent: March 22, 2016Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Amirhasan Nourbakhsh, Bart Soree, Marc Heyns, Tarun Kumar Agarwal
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Patent number: 9184270Abstract: A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.Type: GrantFiled: March 31, 2014Date of Patent: November 10, 2015Assignees: IMEC, Katholieke Universiteit Leuven, K.U.LEUVEN R&DInventors: Amirhasan Nourbakhsh, Marc Heyns, Stefan De Gendt
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Publication number: 20150171167Abstract: A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.Type: ApplicationFiled: December 16, 2014Publication date: June 18, 2015Inventors: Amirhasan Nourbakhsh, Bart Soree, Marc Heyns, Tarun Kumar Agarwal
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Publication number: 20140299841Abstract: A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.Type: ApplicationFiled: March 31, 2014Publication date: October 9, 2014Inventors: Amirhasan Nourbakhsh, Marc Heyns, Stefan De Gendt
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Publication number: 20130313522Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.Type: ApplicationFiled: March 29, 2013Publication date: November 28, 2013Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: Amirhasan Nourbakhsh, Mirco Cantoro, Cedric Huyghebaert, Marc Heyns, Stefan De Gendt