Patents by Inventor Amit Agarwal

Amit Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180145663
    Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Applicant: INTEL CORPORATION
    Inventors: Amit Agarwal, Steven K. Hsu, Simeon Realov, Iqbal R. Rajwani, Ram K. Krishnamurthy
  • Patent number: 9967230
    Abstract: The present disclosure is directed to allocating communication resources via information technology infrastructure. A system can provide a communication tag and an analytics tag for integration in a web site. The system can receive a request to allocate a phone number generated based on an interaction between the communication tag and the analytics tag. The request can include the communication endpoint identifier, the site identifier for the web site, and a bucket identifier formed from bucketing criteria corresponding to a network activity session of the computing device. The system can determine a virtual phone number to assign to a combination of the values of the fields provided in the request, and create a link between the assigned virtual number and the combination. The system can provide the assigned virtual phone number to the computing device that initiated the request.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 8, 2018
    Assignee: Google LLC
    Inventors: Ahmed Mohamed Hassan Osman Akef, Anshul Kothari, Daniel Andersson, Amit Agarwal, Anshul Kundani, Narendra Kumar Singhal
  • Patent number: 9960753
    Abstract: Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy
  • Patent number: 9953182
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Patent number: 9948888
    Abstract: Computer-implemented techniques can include in response to a request, establishing, between a first and second computing devices, a video chat session. The techniques can include receiving, by the first computing device and from a user, an input to operate a casting device in an output mode for the video chat session, the casting device being connected to a display and, in response to receiving the input, transmitting, to the casting device, configuration information that causes the casting device to (i) receive, from the other computing device, first audio/video information for the video chat session and (ii) output, via the display, the first audio/video information during the output mode. The techniques can also include capturing, by the first computing device, second audio/video information for the video chat session and transmitting, to the other computing device, the second audio/video information.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 17, 2018
    Assignee: GOOGLE LLC
    Inventor: Amit Agarwal
  • Publication number: 20180102947
    Abstract: The present disclosure is directed to a technique for reduction of latency in network traffic data transmissions. The system parses an online document to determine a messaging identifier used to communicate over an asynchronous network-based communication channel with a content provider device. The system assembles a first instance of the online content item with the messaging identifier. An intermediary appliance located on the asynchronous network-based communication channel in between the first computing device and the content provider device intercepts data packets including the electronic message The system determines a quality of the asynchronous network-based communication channel. The system blocks insertion of the messaging identifier in a second instance of the online content item prior to transmission of the second instance of the online content item to a second computing device to reduce latency by preventing additional messages from being sent to the messaging identifier.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 12, 2018
    Inventors: Gaurav Ravindra Bhaya, Amit Agarwal, Varun Soundararajan
  • Patent number: 9934404
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Patent number: 9934405
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Publication number: 20180091150
    Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy
  • Publication number: 20180075493
    Abstract: The present disclosure is directed to systems and methods of providing content. A server can generate a request for a push content item for an account identifier linked with a computing device. The server can establish a push auction for the account identifier with multiple candidate push content items. The server can determine an auction score for each candidate push content item and select a push content item therefrom based on the auction score. The server can determine a parameter for the account identifier and control delivery of the selected push content item based on a delivery control policy. The server can compare a value of the parameter with a threshold value to authorize the push content item. The server can provide the selected and authorized push content item for presentation in a push content slot via the computing device linked to the account identifier.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Applicant: Google LLC
    Inventors: Amit Agarwal, Surojit Chatterjee, Gaurav Bhaya, Anshul Kothari, Vibhor Nanavati
  • Publication number: 20180069538
    Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 8, 2018
    Inventors: Amit Agarwal, Steven K. Hsu, Ram K. Krishnamurthy
  • Publication number: 20180062625
    Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Inventors: Amit Agarwal, Steven K. Hsu, Simeon Realov, Ram K. Krishnamurthy
  • Publication number: 20180062658
    Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 1, 2018
    Inventors: Steven K. Hsu, Amit Agarwal, Iqbal R. Rajwani, Simeon Realov, Ram K. Krishnamurthy
  • Publication number: 20180032360
    Abstract: Disclosed aspects relate to rearrangement management for a shared pool of configurable computing resources including a source asset, a target asset, and a memory device having a set of data. A first subset of the set of data on the memory device may be locked with respect to modification. A first set of logical address identifiers for the first subset of the set of data on the memory device may be identified in a hypervisor mapping table in a first set of source entries for the source asset. The first set of logical address identifiers for the first subset of the set of data on the memory device may be established in the hypervisor mapping table in a first set of target entries for the target asset. The first subset of the set of data on the memory device may be unlocked with respect to modification.
    Type: Application
    Filed: July 26, 2016
    Publication date: February 1, 2018
    Inventors: Amit Agarwal, Uma Maheswara R. Chandolu, Chetan L. Gaonkar, Shailaja Mallya
  • Publication number: 20180020096
    Abstract: The present disclosure is directed to syncing data related to voice calls via dynamically assigned virtual phone numbers. A system receives a voice call entry from a content provider. The system access a lot data structure to parse the log data structure. The system matches a device identifier of the voice call entry with a device identifier of the log entry. The system determines that a predetermined threshold is satisfied by a time or duration of the log entry. The system retrieves a virtual phone number from the log entry. The system performs a lookup to determine a content item impression identifier. The system stores data provided via the voice call entry.
    Type: Application
    Filed: September 27, 2017
    Publication date: January 18, 2018
    Inventors: Seung Yi, Anshul Kothari, Amit Agarwal, Monica Chawathe Lenart, Ajit Apte
  • Patent number: 9859876
    Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Amit Agarwal, Steven K. Hsu, Simeon Realov, Iqbal R. Rajwani, Ram K. Krishnamurthy
  • Publication number: 20170359054
    Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 14, 2017
    Inventors: Steven K. HSU, Amit AGARWAL, Simeon REALOV
  • Publication number: 20170352408
    Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Amit AGARWAL, Steven K. HSU, Sri Harsha CHODAY
  • Publication number: 20170344752
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 30, 2017
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Publication number: 20170344753
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 30, 2017
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu