Patents by Inventor Amit Badole

Amit Badole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171856
    Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
  • Publication number: 20190036803
    Abstract: An apparatus is provided which comprises: a first network interface (NI) to receive data from a source; a second NI coupled to a target; and a circuitry to generate a sequence of source timestamps and a sequence of target timestamps, wherein the first NI is to receive the sequence of source timestamps, and associate a first source timestamp of the sequence of source timestamps with the data, and wherein the second NI is to receive: the data with the first source timestamp from the first NI and the sequence of target timestamps from the circuitry, the second NI to generate a timestamp for the data, based at least in part on the first source timestamp and a first target timestamp of the sequence of target timestamps.
    Type: Application
    Filed: December 7, 2017
    Publication date: January 31, 2019
    Applicant: Intel IP Corporation
    Inventors: Pradeep Kumar, Amit Badole, Arumugam Vijayaraman, Helmut Reinig, Patrik Eder, Vladimir Todorov, Abhiram Anantharamu
  • Publication number: 20120321079
    Abstract: A system and method for generating round keys used for encrypting and decrypting an input text block. A received cipher key is used to generate round keys that include round key words. Two round key words are generated at the same timebased on the word lengths of the input text block and the cipher key. The generation of round keys may be paused depending on the word lengths of the input text block and the cipher key.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 20, 2012
    Applicant: Freescale Semiconductor, INC
    Inventor: Amit Badole
  • Patent number: 7561689
    Abstract: An apparatus is disclosed for generating keys having one of a number of key sizes. Memory sections of a memory element are adapted to store a portion of a key. The memory element has a size at least as large as a largest key size of a number of key sizes, the key having a size of one of the plurality of key sizes. Key generation logic is adapted to generate intermediate key results for the key by operating on values from the memory sections and from the intermediate key results. Key selection logic is adapted to route selected intermediate key results to selected ones of the memory sections. The control logic is adapted to determine the size of the key and, based at least partially on the size of the key, to select the selected intermediate key results and the selected ones of the memory sections. The selected intermediate key results comprise some or all of the key.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: July 14, 2009
    Assignee: Agere Systems Inc.
    Inventors: Prasad Avasarala, Amit Badole, Anil Narayan Nair, Rahul Vijay Wagh
  • Publication number: 20060002549
    Abstract: An apparatus is disclosed for generating keys having one of a number of key sizes. Memory sections of a memory element are adapted to store a portion of a key. The memory element has a size at least as large as a largest key size of a number of key sizes, the key having a size of one of the plurality of key sizes. Key generation logic is adapted to generate intermediate key results for the key by operating on values from the memory sections and from the intermediate key results. Key selection logic is adapted to route selected intermediate key results to selected ones of the memory sections. The control logic is adapted to determine the size of the key and, based at least partially on the size of the key, to select the selected intermediate key results and the selected ones of the memory sections. The selected intermediate key results comprise some or all of the key.
    Type: Application
    Filed: June 17, 2004
    Publication date: January 5, 2006
    Inventors: Prasad Avasarala, Amit Badole, Anil Nair, Rahul Wagh