Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.

Abstract: A storage system, including a host device; and a storage device including a nonvolatile memory and at least one processor configured to implement a storage internal protection (SIP) module, wherein the SIP module is configured to: obtain, from the host device, a plurality of storage commands corresponding to the nonvolatile memory, filter the plurality of storage commands to obtain a filtered plurality of storage commands, apply information about the filtered plurality of storage commands to a machine-learning cryptocurrency mining (CM) detection algorithm, and based on the machine-learning CM detection algorithm indicating that a CM operation is detected, provide a notification to the host device.

Abstract: A storage system, including a host device; and a storage device including a memory and at least one processor configured to implement a storage internal protection (SIP) module, wherein the SIP module is configured to: obtain, from the host device, a plurality of storage commands corresponding to the memory, filter the plurality of storage commands to obtain a filtered plurality of storage commands, apply information about the filtered plurality of storage commands to a machine-learning ransomware detection algorithm, and based on the machine-learning ransomware detection algorithm indicating that a ransomware operation is detected, provide a notification to the host device.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: A processing circuit is configured to: construct a first locator polynomial for a Reed-Solomon codeword to identify locations of erasures in the Reed-Solomon codeword; determine a first syndrome of the Reed-Solomon codeword; calculate a first error evaluator polynomial from the first syndrome and the first locator polynomial; and perform error detection based on the first error evaluator polynomial to determine presence of errors in the Reed-Solomon codeword. When presence of errors in the Reed-Solomon codeword is not detected in the error detection, the processing circuit bypasses updating the first locator polynomial and proceeds to completing decoding of the Reed-Solomon codeword, but when presence of errors in the Reed-Solomon codeword is detected in the error detection, the system first updates the first locator polynomial to a second locator polynomial in a process with reduced complexity compared to the common one, before completing decoding of the Reed-Solomon codeword.

Abstract: A storage system, including a storage device configured to store a plurality of encoded values, wherein each value of the plurality of encoded values has a predetermined value length and is within a predetermined range, and wherein the predetermined range is not a power of 2; and at least one processor configured to: group the plurality of encoded values into a codeword; obtain a plurality of bit chunks, wherein each bit chunk of the plurality of bit chunks represents a corresponding encoded value of the plurality of encoded values, and wherein a length of the each bit chunk is selected from among one or more predetermined bit chunk lengths which are determined based on the predetermined range; select a variable-length prefix from among a plurality of variable-length prefixes, wherein the variable-length prefix indicates bit chunk lengths of the plurality of bit chunks; obtain a compressed codeword including the variable-length prefix and the plurality of bit chunks; and decode the plurality of encoded values

Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector ?v(l) of soft information from a parent node; computing a vector ?vl(l) of soft information for a left child of node v; providing node v with a vector ?vl(l) of hard decisions from the left child and using it with ?v(l) to create a soft information vector ?vr(l) and passing it to a right child of node v; providing node v with a vector ?vr(l) of hard decisions from its right child and using it with ?vl(l) to create a hard decision vector, ?v of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Abstract: A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector ?v(l) of soft information from a parent node; computing a vector ?vl(l) of soft information for a left child of node v; providing node v with a vector ?vl(l) of hard decisions from the left child and using it with ?v(l) to create a soft information vector ?vr(l) and passing it to a right child of node v; providing node v with a vector ?vr(l) of hard decisions from its right child and using it with ?vl(l) to create a hard decision vector, ?v of hard decisions, and passing it to its parent node; updating, when v is a ith leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Abstract: A memory system includes a plurality of memory cells each storing multiple bits and a memory controller having a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host to generate first raw data of a first page and second raw data of a second page adjacent to the first page. The memory controller is further configured to perform a hard decision (HD) decoding on the first raw data to generate first decoded data. The processor is configured to apply the first decoded data and the second raw data as input features to a machine learning algorithm to generate reliability information. The memory controller is further configured to perform a HD decoding on the second raw data using the reliability information to generate second decoded data.

Abstract: A memory system includes a plurality of memory cells each storing multiple bits and a memory controller having a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host to generate first raw data of a first page and second raw data of a second page adjacent to the first page. The memory controller is further configured to perform a hard decision (HD) decoding on the first raw data to generate first decoded data. The processor is configured to apply the first decoded data and the second raw data as input features to a machine learning algorithm to generate reliability information. The memory controller is further configured to perform a HD decoding on the second raw data using the reliability information to generate second decoded data.

Abstract: A storage system, including a storage device configured to store a plurality of encoded values, wherein each value of the plurality of encoded values has a predetermined value length and is within a predetermined range, and wherein the predetermined range is not a power of 2; and at least one processor configured to: group the plurality of encoded values into a codeword; obtain a plurality of bit chunks, wherein each bit chunk of the plurality of bit chunks represents a corresponding encoded value of the plurality of encoded values, and wherein a length of the each bit chunk is selected from among one or more predetermined bit chunk lengths which are determined based on the predetermined range; select a variable-length prefix from among a plurality of variable-length prefixes, wherein the variable-length prefix indicates bit chunk lengths of the plurality of bit chunks; obtain a compressed codeword including the variable-length prefix and the plurality of bit chunks; and decode the plurality of encoded values

Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Abstract: An storage device is provided. The storage device includes: a nonvolatile memory; and at least one processor configured to: obtain an input symbol to be stored in a target memory cell among a plurality of memory cells of the nonvolatile memory; obtain cell features of the plurality of memory cells; determine a target voltage for the target memory cell based on the input symbol and the cell features of the plurality of memory cells; and provide the target voltage to the target memory cell.

Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

Abstract: Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

Abstract: A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has ?=t+r errors for some r?1; computing a minimal monotone basis {?i(x)}1?i?r+1?F[x] of an affine space V={?(x)?F[x]:?(x)·S(x)=??(x) (mod x2t), ?(0)=1, deg(?(x)?t+r}, wherein ?(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A?(?j(?i))i?[w],j?[r+1], wherein W={?1, . . . , ?w} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.