Patents by Inventor Amit Bhatia
Amit Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12710768Abstract: A seeker configured to generate an aimpoint, wherein the seeker captures image frames associated with a forward-looking perspective of the platform that potentially contain a target and is configured to apply a first method of image processing to the image frames, the first method of image processing not requiring the use of a target model, to finalize a pixel area that matches characteristics associated with the target, to generate at least one track point corresponding to a distinctive portion of the target, and to generate an aimpoint associated with the target. While iteratively applying the first method, the seeker may also store the at least one image frame that matches characteristics associated with the target, creating a reference image frame containing the target; determine at least one track point on the target; search for and update the track points in a subsequent image frame; and search for new track points in the subsequent image frame, creating an updated target model.Type: GrantFiled: April 16, 2024Date of Patent: August 18, 2026Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Amit Bhatia, Peter Dusaitis, Jeffrey L. Jew, Tao Wang, Umang R. Patel
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Publication number: 20260161425Abstract: An apparatus comprising a first large language model (LLM) system configured to receive a natural language specification of a system design and generate a first description of the system design in a temporal logic language responsive to the natural language specification. A second LLM system is configured to receive the natural language specification and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM is configured to generate verification drivers for the system design responsive to the first description of the system design. A formal verification (FV) tool is configured to indicate whether the system design passes or fails responsive to the first description of the system design in a temporal logic language.Type: ApplicationFiled: December 9, 2024Publication date: June 11, 2026Inventors: Mark Moulin, Amit Bhatia
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Publication number: 20260161870Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM configured to generate verification drivers for the system design. A formal verification (FV) tool configured to determine whether a model of the system design passes or fails. The FV tool is further configured to generate a property witness template and an optimal witness template.Type: ApplicationFiled: December 9, 2024Publication date: June 11, 2026Inventors: Mark Moulin, Amit Bhatia
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Publication number: 20260161426Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language. A second LLM system is configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A generator and compiler is configured to generate finite state machines. At least one finite state machine (FSM) generated by the generator and compiler is configured to analyze operation of the system design using each of the at least one FSM including optimization properties. A formal verification (FV) tool is configured to determine whether the system design passes or fails responsive to the first description of the system design in the temporal logic language.Type: ApplicationFiled: December 9, 2024Publication date: June 11, 2026Inventors: Mark Moulin, Amit Bhatia
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Publication number: 20260161872Abstract: An apparatus for performing formal verification of a system design, comprising a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A finite state machine (FSM) is configured to verify the system design responsive to the second description of the system design in the temporal logic. A formal verification (FV) tool is configured to indicate whether the system design passes or fails, wherein the FV tool is further configured to provide a verification coverage estimation of a model implemented by the FV tool using a finite elements method (FEM) triangulation mesh.Type: ApplicationFiled: December 9, 2024Publication date: June 11, 2026Inventors: Mark Moulin, Amit Bhatia
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Publication number: 20250217554Abstract: A method of designing a component includes the steps of 1) inputting operator desired performance of a final component into a neural function-learning based module, and utilizing the neural function-learning based module to reach desired structural features for the component, 2) generating a physically realizable design in a design realization module based on the structural features and 3) evaluating the physically realizable design in an evaluation module, and utilizing evaluation module output to determine performance results for the physically realizable design. A system is also disclosed.Type: ApplicationFiled: November 8, 2024Publication date: July 3, 2025Inventors: Amit Bhatia, Kathryn L. Kirsch, Claudio Pinello
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Patent number: 11962346Abstract: An apparatus includes a photonic integrated circuit having an optical phased array, where the optical phased array includes multiple unit cells. Each unit cell includes (i) an antenna element configured to transmit or receive optical signals and (ii) a phase modulator configured to modify phases of the optical signals being transmitted or received by the antenna element. The apparatus also includes a gyroscopic sensor configured to sense movement of the photonic integrated circuit, where at least a portion of the gyroscopic sensor is integrated within the photonic integrated circuit.Type: GrantFiled: August 15, 2022Date of Patent: April 16, 2024Assignee: Raytheon CompanyInventors: Stephen P. Palese, Duane D. Smith, Amit Bhatia
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Publication number: 20240056184Abstract: An apparatus includes a photonic integrated circuit having an optical phased array, where the optical phased array includes multiple unit cells. Each unit cell includes (i) an antenna element configured to transmit or receive optical signals and (ii) a phase modulator configured to modify phases of the optical signals being transmitted or received by the antenna element. The apparatus also includes a gyroscopic sensor configured to sense movement of the photonic integrated circuit, where at least a portion of the gyroscopic sensor is integrated within the photonic integrated circuit.Type: ApplicationFiled: August 15, 2022Publication date: February 15, 2024Inventors: Stephen P. Palese, Duane D. Smith, Amit Bhatia
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Patent number: 11544931Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.Type: GrantFiled: November 20, 2020Date of Patent: January 3, 2023Assignee: OTIS ELEVATOR COMPANYInventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
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Patent number: 11378646Abstract: The discriminability of an RF fingerprint is increased by “abstracting,” “enhancing,” and “reconstructing” a digital signal before it is transmitted, where the abstraction is a reversible nonlinear compression, the enhancement is a modification of the abstracted data, and the reconstruction is a mapping-back of the abstraction. During a training phase, for each individual RF transmitter, RF fingerprints are analyzed and candidate enhancements are modified until a successful enhancement is identified that provides satisfactory discriminability improvement with minimal signal degradation. The successful enhancement is implemented in the RF transmitter, and the RF fingerprint is communicated to receivers for subsequent detection and verification. Reinforcement learning can direct modifications to the candidate enhancements. The abstraction can implement a deep generative model such as an auto-encoder.Type: GrantFiled: August 13, 2019Date of Patent: July 5, 2022Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Scott A Kuzdeba, Amit Bhatia, David J. Couto, Denis Garagic, John A. Tranquilli, Jr.
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Neural network kernels for signal processing in lieu of digital signal processing in radio receivers
Patent number: 11342946Abstract: An artifact-suppressing neural network (NN) kernel comprising at least one neural network, implemented in replacement of a DSP, provides comparable or better performance under non-edge conditions, and superior performance under edge conditions, due to the ease of updating the NN kernel training without enlarging its computational footprint or latency to address a new edge condition. In embodiments, the NN kernel can be implemented in a field programmable gate array (FPGA) or application specific integrated circuit (ASIC), which can be configured as a direct DSP replacement. In various embodiments, the NN kernel training can be updated in near real time when a new edge condition is encountered in the field. The NN kernel can include DCC lower layers and dense upper layers. Initial NN kernel training can require fewer examples. Example embodiments include a noise suppression NN kernel and a modem NN kernel.Type: GrantFiled: March 22, 2021Date of Patent: May 24, 2022Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Amit Bhatia, Joseph M. Carmack, Scott A Kuzdeba, Joshua W. Robinson -
Publication number: 20210374424Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.Type: ApplicationFiled: November 20, 2020Publication date: December 2, 2021Inventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
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Publication number: 20210048507Abstract: The discriminability of an RF fingerprint is increased by “abstracting,” “enhancing,” and “reconstructing” a digital signal before it is transmitted, where the abstraction is a reversible nonlinear compression, the enhancement is a modification of the abstracted data, and the reconstruction is a mapping-back of the abstraction. During a training phase, for each individual RF transmitter, RF fingerprints are analyzed and candidate enhancements are modified until a successful enhancement is identified that provides satisfactory discriminability improvement with minimal signal degradation. The successful enhancement is implemented in the RF transmitter, and the RF fingerprint is communicated to receivers for subsequent detection and verification. Reinforcement learning can direct modifications to the candidate enhancements. The abstraction can implement a deep generative model such as an auto-encoder.Type: ApplicationFiled: August 13, 2019Publication date: February 18, 2021Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.Inventors: Scott A. Kuzdeba, Amit Bhatia, David J. Couto, Denis Garagic, John A. Tranquilli, JR.
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Patent number: 10514301Abstract: A method for monitoring wellsite equipment may include producing a digital image and a thermal image of the wellsite equipment; identifying one or more equipment units in the digital image; overlaying the thermal image on the one or more identified equipment units in the digital image to thermally map the one or more identified equipment units; and analyzing temperature conditions of at least a first identified equipment unit.Type: GrantFiled: June 5, 2015Date of Patent: December 24, 2019Assignee: SCHLUMBERGER TECHNOLOGY CORPORATIONInventors: Rajesh Luharuka, Amit Bhatia, Garud Bindiganavale Sridhar, Jonathan Wun Shiung Chong
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Patent number: 10005564Abstract: An autonomous cargo handling system is provided. The autonomous cargo handling system may comprise one or more sensing agents in electronic communication with each other. One or more of the sensing agents may be configured to monitor a sensing zone in a cargo deck to detect objects traveling through the sensing zone. In response to detecting an object, one or more sensing agents may determine an object property based on the detected object. One or more sensing agents may generate an object model based on the determined object properties. The sensing agents may also determine whether the detected object is a unit load device (ULD) or a non-ULD object based on the object property and/or the object model.Type: GrantFiled: May 5, 2017Date of Patent: June 26, 2018Assignee: GOODRICH CORPORATIONInventors: Amit Bhatia, Zamira Daw Perez, Alessandro Pinto, Julian C. Ryde
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Publication number: 20170322086Abstract: A method for monitoring wellsite equipment may include producing a digital image and a thermal image of the wellsite equipment; identifying one or more equipment units in the digital image; overlaying the thermal image on the one or more identified equipment units in the digital image to thermally map the one or more identified equipment units; and analyzing temperature conditions of at least a first identified equipment unit.Type: ApplicationFiled: June 5, 2015Publication date: November 9, 2017Inventors: Rajesh LUHARUKA, Amit BHATIA, Garud Bindiganavale SRIDHAR, Jonathan Wun Shiung CHONG
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Patent number: 9698913Abstract: A phase-modulated optical link and methods are provided to suppress distortions in phase-encoded analog photonic links. The phase-modulated optical link includes a distortion compensation element. The distortion compensation element includes an optical comb generator that is seeded by a phase-encoded optical signal. The methods include generating an optical comb seeded by a portion of a phase-encoded optical signal and isolating desired peaks to be combined with a separate portion of the phase-encoded optical signal.Type: GrantFiled: June 8, 2015Date of Patent: July 4, 2017Assignee: THE JOHN HOPKINS UNIVERSITYInventors: Mark Foster, Amit Bhatia
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Publication number: 20150358086Abstract: A phase-modulated optical link and methods are provided to suppress distortions in phase-encoded analog photonic links. The phase-modulated optical link includes a distortion compensation element. The distortion compensation element includes an optical comb generator that is seeded by a phase-encoded optical signal. The methods include generating an optical comb seeded by a portion of a phase-encoded optical signal and isolating desired peaks to be combined with a separate portion of the phase-encoded optical signal.Type: ApplicationFiled: June 8, 2015Publication date: December 10, 2015Inventors: MARK FOSTER, Amit Bhatia
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Patent number: D1126799Type: GrantFiled: October 24, 2024Date of Patent: May 19, 2026Assignee: Colgate-Palmolive CompanyInventors: Indrani Banerjee, Donghui Wu, Bryan Lee, Mark Guirguis, Amit Bhatia, Nicolas Ochoa, Santiago Acosta, Anthony Baxter