Patents by Inventor Amit Bhatia

Amit Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12710768
    Abstract: A seeker configured to generate an aimpoint, wherein the seeker captures image frames associated with a forward-looking perspective of the platform that potentially contain a target and is configured to apply a first method of image processing to the image frames, the first method of image processing not requiring the use of a target model, to finalize a pixel area that matches characteristics associated with the target, to generate at least one track point corresponding to a distinctive portion of the target, and to generate an aimpoint associated with the target. While iteratively applying the first method, the seeker may also store the at least one image frame that matches characteristics associated with the target, creating a reference image frame containing the target; determine at least one track point on the target; search for and update the track points in a subsequent image frame; and search for new track points in the subsequent image frame, creating an updated target model.
    Type: Grant
    Filed: April 16, 2024
    Date of Patent: August 18, 2026
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Amit Bhatia, Peter Dusaitis, Jeffrey L. Jew, Tao Wang, Umang R. Patel
  • Publication number: 20260161425
    Abstract: An apparatus comprising a first large language model (LLM) system configured to receive a natural language specification of a system design and generate a first description of the system design in a temporal logic language responsive to the natural language specification. A second LLM system is configured to receive the natural language specification and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM is configured to generate verification drivers for the system design responsive to the first description of the system design. A formal verification (FV) tool is configured to indicate whether the system design passes or fails responsive to the first description of the system design in a temporal logic language.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 11, 2026
    Inventors: Mark Moulin, Amit Bhatia
  • Publication number: 20260161870
    Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM configured to generate verification drivers for the system design. A formal verification (FV) tool configured to determine whether a model of the system design passes or fails. The FV tool is further configured to generate a property witness template and an optimal witness template.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 11, 2026
    Inventors: Mark Moulin, Amit Bhatia
  • Publication number: 20260161426
    Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language. A second LLM system is configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A generator and compiler is configured to generate finite state machines. At least one finite state machine (FSM) generated by the generator and compiler is configured to analyze operation of the system design using each of the at least one FSM including optimization properties. A formal verification (FV) tool is configured to determine whether the system design passes or fails responsive to the first description of the system design in the temporal logic language.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 11, 2026
    Inventors: Mark Moulin, Amit Bhatia
  • Publication number: 20260161872
    Abstract: An apparatus for performing formal verification of a system design, comprising a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A finite state machine (FSM) is configured to verify the system design responsive to the second description of the system design in the temporal logic. A formal verification (FV) tool is configured to indicate whether the system design passes or fails, wherein the FV tool is further configured to provide a verification coverage estimation of a model implemented by the FV tool using a finite elements method (FEM) triangulation mesh.
    Type: Application
    Filed: December 9, 2024
    Publication date: June 11, 2026
    Inventors: Mark Moulin, Amit Bhatia
  • Publication number: 20250217554
    Abstract: A method of designing a component includes the steps of 1) inputting operator desired performance of a final component into a neural function-learning based module, and utilizing the neural function-learning based module to reach desired structural features for the component, 2) generating a physically realizable design in a design realization module based on the structural features and 3) evaluating the physically realizable design in an evaluation module, and utilizing evaluation module output to determine performance results for the physically realizable design. A system is also disclosed.
    Type: Application
    Filed: November 8, 2024
    Publication date: July 3, 2025
    Inventors: Amit Bhatia, Kathryn L. Kirsch, Claudio Pinello
  • Patent number: 11962346
    Abstract: An apparatus includes a photonic integrated circuit having an optical phased array, where the optical phased array includes multiple unit cells. Each unit cell includes (i) an antenna element configured to transmit or receive optical signals and (ii) a phase modulator configured to modify phases of the optical signals being transmitted or received by the antenna element. The apparatus also includes a gyroscopic sensor configured to sense movement of the photonic integrated circuit, where at least a portion of the gyroscopic sensor is integrated within the photonic integrated circuit.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 16, 2024
    Assignee: Raytheon Company
    Inventors: Stephen P. Palese, Duane D. Smith, Amit Bhatia
  • Publication number: 20240056184
    Abstract: An apparatus includes a photonic integrated circuit having an optical phased array, where the optical phased array includes multiple unit cells. Each unit cell includes (i) an antenna element configured to transmit or receive optical signals and (ii) a phase modulator configured to modify phases of the optical signals being transmitted or received by the antenna element. The apparatus also includes a gyroscopic sensor configured to sense movement of the photonic integrated circuit, where at least a portion of the gyroscopic sensor is integrated within the photonic integrated circuit.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Stephen P. Palese, Duane D. Smith, Amit Bhatia
  • Patent number: 11544931
    Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 3, 2023
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
  • Patent number: 11378646
    Abstract: The discriminability of an RF fingerprint is increased by “abstracting,” “enhancing,” and “reconstructing” a digital signal before it is transmitted, where the abstraction is a reversible nonlinear compression, the enhancement is a modification of the abstracted data, and the reconstruction is a mapping-back of the abstraction. During a training phase, for each individual RF transmitter, RF fingerprints are analyzed and candidate enhancements are modified until a successful enhancement is identified that provides satisfactory discriminability improvement with minimal signal degradation. The successful enhancement is implemented in the RF transmitter, and the RF fingerprint is communicated to receivers for subsequent detection and verification. Reinforcement learning can direct modifications to the candidate enhancements. The abstraction can implement a deep generative model such as an auto-encoder.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: July 5, 2022
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Scott A Kuzdeba, Amit Bhatia, David J. Couto, Denis Garagic, John A. Tranquilli, Jr.
  • Patent number: 11342946
    Abstract: An artifact-suppressing neural network (NN) kernel comprising at least one neural network, implemented in replacement of a DSP, provides comparable or better performance under non-edge conditions, and superior performance under edge conditions, due to the ease of updating the NN kernel training without enlarging its computational footprint or latency to address a new edge condition. In embodiments, the NN kernel can be implemented in a field programmable gate array (FPGA) or application specific integrated circuit (ASIC), which can be configured as a direct DSP replacement. In various embodiments, the NN kernel training can be updated in near real time when a new edge condition is encountered in the field. The NN kernel can include DCC lower layers and dense upper layers. Initial NN kernel training can require fewer examples. Example embodiments include a noise suppression NN kernel and a modem NN kernel.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 24, 2022
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Amit Bhatia, Joseph M. Carmack, Scott A Kuzdeba, Joshua W. Robinson
  • Publication number: 20210374424
    Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 2, 2021
    Inventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
  • Publication number: 20210048507
    Abstract: The discriminability of an RF fingerprint is increased by “abstracting,” “enhancing,” and “reconstructing” a digital signal before it is transmitted, where the abstraction is a reversible nonlinear compression, the enhancement is a modification of the abstracted data, and the reconstruction is a mapping-back of the abstraction. During a training phase, for each individual RF transmitter, RF fingerprints are analyzed and candidate enhancements are modified until a successful enhancement is identified that provides satisfactory discriminability improvement with minimal signal degradation. The successful enhancement is implemented in the RF transmitter, and the RF fingerprint is communicated to receivers for subsequent detection and verification. Reinforcement learning can direct modifications to the candidate enhancements. The abstraction can implement a deep generative model such as an auto-encoder.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventors: Scott A. Kuzdeba, Amit Bhatia, David J. Couto, Denis Garagic, John A. Tranquilli, JR.
  • Patent number: 10514301
    Abstract: A method for monitoring wellsite equipment may include producing a digital image and a thermal image of the wellsite equipment; identifying one or more equipment units in the digital image; overlaying the thermal image on the one or more identified equipment units in the digital image to thermally map the one or more identified equipment units; and analyzing temperature conditions of at least a first identified equipment unit.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 24, 2019
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Rajesh Luharuka, Amit Bhatia, Garud Bindiganavale Sridhar, Jonathan Wun Shiung Chong
  • Patent number: 10005564
    Abstract: An autonomous cargo handling system is provided. The autonomous cargo handling system may comprise one or more sensing agents in electronic communication with each other. One or more of the sensing agents may be configured to monitor a sensing zone in a cargo deck to detect objects traveling through the sensing zone. In response to detecting an object, one or more sensing agents may determine an object property based on the detected object. One or more sensing agents may generate an object model based on the determined object properties. The sensing agents may also determine whether the detected object is a unit load device (ULD) or a non-ULD object based on the object property and/or the object model.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: June 26, 2018
    Assignee: GOODRICH CORPORATION
    Inventors: Amit Bhatia, Zamira Daw Perez, Alessandro Pinto, Julian C. Ryde
  • Publication number: 20170322086
    Abstract: A method for monitoring wellsite equipment may include producing a digital image and a thermal image of the wellsite equipment; identifying one or more equipment units in the digital image; overlaying the thermal image on the one or more identified equipment units in the digital image to thermally map the one or more identified equipment units; and analyzing temperature conditions of at least a first identified equipment unit.
    Type: Application
    Filed: June 5, 2015
    Publication date: November 9, 2017
    Inventors: Rajesh LUHARUKA, Amit BHATIA, Garud Bindiganavale SRIDHAR, Jonathan Wun Shiung CHONG
  • Patent number: 9698913
    Abstract: A phase-modulated optical link and methods are provided to suppress distortions in phase-encoded analog photonic links. The phase-modulated optical link includes a distortion compensation element. The distortion compensation element includes an optical comb generator that is seeded by a phase-encoded optical signal. The methods include generating an optical comb seeded by a portion of a phase-encoded optical signal and isolating desired peaks to be combined with a separate portion of the phase-encoded optical signal.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 4, 2017
    Assignee: THE JOHN HOPKINS UNIVERSITY
    Inventors: Mark Foster, Amit Bhatia
  • Publication number: 20150358086
    Abstract: A phase-modulated optical link and methods are provided to suppress distortions in phase-encoded analog photonic links. The phase-modulated optical link includes a distortion compensation element. The distortion compensation element includes an optical comb generator that is seeded by a phase-encoded optical signal. The methods include generating an optical comb seeded by a portion of a phase-encoded optical signal and isolating desired peaks to be combined with a separate portion of the phase-encoded optical signal.
    Type: Application
    Filed: June 8, 2015
    Publication date: December 10, 2015
    Inventors: MARK FOSTER, Amit Bhatia
  • Patent number: D1126799
    Type: Grant
    Filed: October 24, 2024
    Date of Patent: May 19, 2026
    Assignee: Colgate-Palmolive Company
    Inventors: Indrani Banerjee, Donghui Wu, Bryan Lee, Mark Guirguis, Amit Bhatia, Nicolas Ochoa, Santiago Acosta, Anthony Baxter