Abstract: A method of designing an integrated circuit (IC) chip is discloses. The method includes designing a higher level comprising a plurality of outputs configured to be connected to inputs in a previously-designed macro level, wherein each input in the macro level includes a configurable filler cell. The method also includes calculating if each input includes an antenna violation based on the higher level and the macro level, and configuring each of the filler cells, wherein each filler cell associated with an antenna violation is configured as an antenna diode.