Abstract: A computer-implemented method for layout versus schematic (LVS) checking for a design process of an integrated circuit (IC) is provided. The computer-implemented method includes receiving a layout of the IC at multiple hierarchical levels, receiving a schematic of the IC at the multiple hierarchical levels, establishing a requirement for name matching, scanning the layout and the schematic at least at one of the multiple hierarchical levels and issuing an alert for one or more name inconsistencies identified during the scanning.

Abstract: Providing a parameterized IP algorithm for power reduction across a chip hierarchy including for each input pin at a chip hierarchy level, determining a parameterized diode value only for an indication of an antenna violation, wherein a parameterized diode is scaled to protect a gate; and enabling the parameterized diode with the parameterized diode value. Providing a parameterized IP algorithm also includes placing a placeholder parameterized diode for each input pin; for each IP, converting the IP into a parameterized IP; and upon a determination of no antenna violation, disabling the parameterized diode.

Abstract: A method of designing an integrated circuit (IC) chip is discloses. The method includes designing a higher level comprising a plurality of outputs configured to be connected to inputs in a previously-designed macro level, wherein each input in the macro level includes a configurable filler cell. The method also includes calculating if each input includes an antenna violation based on the higher level and the macro level, and configuring each of the filler cells, wherein each filler cell associated with an antenna violation is configured as an antenna diode.

Abstract: A method of designing an integrated circuit (IC) chip is discloses. The method includes designing a higher level comprising a plurality of outputs configured to be connected to inputs in a previously-designed macro level, wherein each input in the macro level includes a configurable filler cell. The method also includes calculating if each input includes an antenna violation based on the higher level and the macro level, and configuring each of the filler cells, wherein each filler cell associated with an antenna violation is configured as an antenna diode.