Patents by Inventor Amit Chopra

Amit Chopra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9444841
    Abstract: A method for enforcing a network policy is described herein. In the method, a network socket event request from an application executing in a first context is intercepted by an agent prior to the request reaching a transport layer in the first context. A context refers to virtualization software, a physical computer, or a combination of virtualization software and physical computer. In response to the interception of the request, the agent requests a decision on whether to allow or deny the network socket event request to be communicated to a security server executing in a second context that is distinct from the first context. The request for a decision includes an identification of the application. The agent then receives from the security server either an allowance or a denial of the network socket event request, the allowance or denial being based at least in part on the identification of the application and a security policy.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: September 13, 2016
    Assignee: VMware, Inc.
    Inventors: Azeem Feroz, Binyuan Chen, Amit Chopra
  • Publication number: 20160099968
    Abstract: Techniques are disclosed for securing traffic flowing across multi-tenant virtualized infrastructures using group key-based encryption. In one embodiment, an encryption module of a virtual machine (VM) host intercepts layer 2 (L2) frames sent via a virtual NIC (vNIC). The encryption module determines whether the vNIC is connected to a “secure wire,” and invokes an API exposed by a key management module to encrypt the frames using a group key associated with the secure wire, if any. Encryption may be performed for all frames from the vNIC, or according to a policy. In one embodiment, the encryption module may be located at a layer farthest from the vNIC, and encryption may be transparent to both the VM and a virtual switch. Unauthorized network entities which lack the group key cannot decipher the data of encrypted frames, even if they gain access to such frames.
    Type: Application
    Filed: December 10, 2015
    Publication date: April 7, 2016
    Inventors: Amit CHOPRA, Uday MASUREKAR
  • Publication number: 20150363888
    Abstract: Embodiments of the invention are directed to systems, methods and computer program products for use in financial forecast systems, where historical financial data is analyzed for purposes of providing projected financial statements. An exemplary apparatus is configured to receive financial data, from a predetermined period of time in the past that is associated with a business entity requesting to receive projected financial statements, analyze the financial data from the predetermined period of time in the past, and determine based on the analysis a financial forecast for the entity for a predetermined period of time in the future, and provide one or more projected financial statements for the predetermined time period in the future based at least partially on the financial forecast of the entity.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventors: Amit Chopra, Shane Prakash Masih, Ashu Chugh, Prashant Bidkar, Mitasha Navani
  • Publication number: 20140230008
    Abstract: A method for enforcing a network policy is described herein. In the method, a network socket event request from an application executing in a first context is intercepted by an agent prior to the request reaching a transport layer in the first context. A context refers to virtualization software, a physical computer, or a combination of virtualization software and physical computer. In response to the interception of the request, the agent requests a decision on whether to allow or deny the network socket event request to be communicated to a security server executing in a second context that is distinct from the first context. The request for a decision includes an identification of the application. The agent then receives from the security server either an allowance or a denial of the network socket event request, the allowance or denial being based at least in part on the identification of the application and a security policy.
    Type: Application
    Filed: February 14, 2013
    Publication date: August 14, 2014
    Applicant: VMware, Inc.
    Inventors: Azeem Feroz, Binyuan Chen, Amit Chopra
  • Publication number: 20140226820
    Abstract: Techniques are disclosed for securing traffic flowing across multi-tenant virtualized infrastructures using group key-based encryption. In one embodiment, an encryption module of a virtual machine (VM) host intercepts layer 2 (L2) frames sent via a virtual NIC (vNIC). The encryption module determines whether the vNIC is connected to a “secure wire,” and invokes an API exposed by a key management module to encrypt the frames using a group key associated with the secure wire, if any. Encryption may be performed for all frames from the vNIC, or according to a policy. In one embodiment, the encryption module may be located at a layer farthest from the vNIC, and encryption may be transparent to both the VM and a virtual switch. Unauthorized network entities which lack the group key cannot decipher the data of encrypted frames, even if they gain access to such frames.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Applicant: VMWARE, INC.
    Inventors: Amit CHOPRA, Uday MASUREKAR
  • Patent number: 8645894
    Abstract: A circuit design system generates a circuit variant by relocating one or more circuit elements through a user move action on a user interface. When the user move action results in the circuit element traversing a circuit domain boundary, the design system performs one or more operations to form the circuit variant having its initial connectivity with the relocated circuit element without any other user action on the user interface than the user move action. Further, in response to no other action on the user interface than the user move action, analysis tools and reports are initiated so that rapid evaluation of circuit variants may be implemented.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: February 4, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Amit Chopra, Raja Vitra
  • Patent number: 8452679
    Abstract: Apparatus, methods and media for providing a supply chain link performance change indicator. The apparatus may include, and the methods and media may involve a processor module, a receiver module and an output device. The processor module may provide to a user a vector selection control. The receiver module may receive financial data corresponding to the supply chain link. The financial data may include a plurality of vectors. The receiver may receive via the vector selection control a first vector identifier corresponding to a first vector in the plurality of vectors and a second vector identifier corresponding to a second vector in the plurality of vectors. The output device may provide to the user a first supply chain link performance change indicator corresponding to the first vector and a second supply chain link performance change indicator corresponding to the second vector.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 28, 2013
    Assignee: Bank of America Corporation
    Inventors: Amit Chopra, Rachna Gambhir, Shane Prakash Masih, Ashu Chugh, Prashant A. Bidkar
  • Patent number: 8407635
    Abstract: A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Amit Chopra
  • Publication number: 20130054300
    Abstract: Apparatus, methods and media for providing a supply chain link performance change indicator. The apparatus may include, and the methods and media may involve a processor module, a receiver module and an output device. The processor module may provide to a user a vector selection control. The receiver module may receive financial data corresponding to the supply chain link. The financial data may include a plurality of vectors. The receiver may receive via the vector selection control a first vector identifier corresponding to a first vector in the plurality of vectors and a second vector identifier corresponding to a second vector in the plurality of vectors. The output device may provide to the user a first supply chain link performance change indicator corresponding to the first vector and a second supply chain link performance change indicator corresponding to the second vector.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: Bank of America
    Inventors: Amit Chopra, Rachna Gambhir, Shane Prakash Masih, Ashu Chugh, Prashant A. Bidkar
  • Publication number: 20120198408
    Abstract: A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Inventor: Amit Chopra
  • Patent number: 7865857
    Abstract: Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: January 4, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Chopra, Ian Gebbie, Donald O'Riordan, Sumit Arora, Jean-Daniel Sonnard