Patents by Inventor Amit Chowdhary

Amit Chowdhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7337418
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Publication number: 20040010759
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 15, 2004
    Applicant: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Patent number: 6594808
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Patent number: 6148433
    Abstract: In some embodiments, the invention includes a method of regularity extraction including generating a set of templates for a circuit through computer automated operations on a description of the circuit. The method also includes covering the circuit with instances of a subset of the templates. In some embodiments, the set of templates includes single-principal output templates, where a single-principal output templates is a template in which all outputs of the template are in the transitive fanin of a particular output of the template. The set of templates may also include tree templates. In some embodiments, the set of templates is a complete set of templates given certain assumptions including that the set of templates include all maximal templates of involved classes of templates and a template is not generated through permuting gate inputs.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: November 14, 2000
    Assignee: Intel Corporation
    Inventors: Amit Chowdhary, Sudhakar S. J. Kale, Phani K. Saripella, Naresh K. Sehgal, Rajesh K. Gupta