Abstract: The present invention discloses a high stem grafted herbaceous plant. The high stem grafted plant comprises herbaceous scion engrafted upon a rootstock at a predetermined height of at least 7 cm. The present invention further provides novel high stem grafted propagation material and methods for producing the high stem grafted herbaceous plant.

Abstract: The present invention discloses a grafted Calibrachoa plant. The grafted plant comprises a selected rootstock engrafted with a Calibrachoa scion. The present invention further provides novel grafted propagation material and methods for producing the grafted propagation material and grafted Calibrachoa plants.

Abstract: Systems and methods for obstruction detection during autonomous unmanned aerial vehicle landings, including unmanned aerial vehicles equipped with at least one video camera, an image processor that analyzes a feed from the video camera to detect possible obstructions, and an autopilot programmed to abort an autonomous landing if it receives a signal indicating an obstruction was detected. In some examples, the systems and methods are in communication with a ground station to perform obstruction detection analysis instead of performing such processing on board the UAV. In some further examples, the landing area includes a ground-based visual target that the UAV can locate and home in upon from the air.

Abstract: In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.

Abstract: Embodiments of the present invention provide a fast, software-implemented data scrambling system for data communications. For pseudo-random codes that are periodic within a predetermined number of bits, a memory array may be populated with segments of the code, one entry in the array starting at a unique bit position within the code. During data scrambling, a seed code may be used to identify a first entry from the array that should be used for scrambling. Thereafter, subsequent segments may be retrieved by traversing the array in a regular fashion. By calculating the code before use and by populating the array prior to processing of any source data, the system is very fast.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: A method and system for interleaving blocks of data. The method includes partitioning an input bitstream into multiple bitstreams, interleaving the multiple bitstreams into a single bitstream, partitioning the single bitstream into multiple different bitstreams, and shuffling the bits of the different bitstreams. Exemplary applications include the IEEE 802.11a standard interleaver stage.

Abstract: There are presented a method, device and system for allocating spill cells for an instrumentation fragment that is run on a processor that uses a register stack architecture where only one free register is available for such fragment.

Abstract: Briefly, a configurable decoder to decode signals of communication systems is provided. The configurable decoder may include a programmable metric data generator to reconfigure an add-compare-select unit according to a predetermined data structure provided by a desired communication protocol and a programmable traceback unit to provide decoded data according to the desired communication protocol.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.

Abstract: Multiplication of complex numbers is performed utilizing a single adder. A “mult_i” instruction includes a first subinstruction to perform a multiplication by +i to perform a first portion of a complex multiplication. Next, a second subinstruction calls a multiplication by −i, and the same adder is used to write results to an output register. The output register contains the results of the complex multiplication.

Abstract: Embodiments of the present invention provide a fast, software-implemented data scrambling system for data communications. For pseudo-random codes that are periodic within a predetermined number of bits, a memory array may be populated with segments of the code, one entry in the array starting at a unique bit position within the code. During data scrambling, a seed code may be used to identify a first entry from the array that should be used for scrambling. Thereafter, subsequent segments may be retrieved by traversing the array in a regular fashion. By calculating the code before use and by populating the array prior to processing of any source data, the system is very fast.

Abstract: In a method and apparatus for multiplying a complex number in the form of (a+ib), (±1 ±i) the multiplication result is resolved into addition operations providing the real number component of the multiplication result and the coefficient of i in the multiplication result. The addition operations are formed in a plurality of steps, and the terms a and b are combined in each of a pair of arithmetic units in a plurality of steps to provide the real number component and the complex number coefficient. In the preferred form, the multiplication is performed in four pairs of addition, and an operation code determines the signs of each term in each arithmetic unit in each operation.

Abstract: A method and system for interleaving blocks of data. The method includes partitioning an input bitstream into multiple bitstreams, interleaving the multiple bitstreams into a single bitstream, partitioning the single bitstream into multiple different bitstreams, and shuffling the bits of the different bitstreams. Exemplary applications include the IEEE 802.11a standard interleaver stage.

Abstract: A method and apparatus for software implementations of input independent LFSR-based algorithms are provided. In one embodiment, an initial location is identified in a cyclic sequence of entries representing a set of possible output values of a Linear Feedback Shift Register. Based on the initial location and a predefined group size, an initial group of entries is identified in the cyclic sequence of entries. Further, a predefined operation is performed on the initial group of entries in the cyclic sequence and an initial portion of input data. The predefined operation is repeated for each remaining portion of input data and a corresponding group of entries in the cyclic sequence.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.