Patents by Inventor Amit Dhir

Amit Dhir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220342912
    Abstract: Systems, methods, and graphical user interfaces (GUIs) for ingesting and enriching data regarding a plurality of entities are provided. A first data set comprising company data and a second data set comprising customer data are ingested. The first data set is processed to generate a processed data set. The first data set may be processed by applying an entity matching technique, wherein one or more data elements are generated based on whether an entity of the first data set and an entity of the second data set are commonly associated. The first data set may additionally or alternatively be processed by applying a statistical matching technique, wherein one or more predicted data elements are generated based on similarity between an entity of the first data set and one or more entities of the second data set.
    Type: Application
    Filed: January 19, 2022
    Publication date: October 27, 2022
    Applicant: PricewaterhouseCoopers LLP
    Inventors: Amit DHIR, Henry HUANG, Michael REID, Pradnesh DESHMUKH, Vasundhara RUNGTA, Prachi AGRAWAL, Pranati DANG, Tarun SHARMA, Vasudeva SANKARANARAYANAN, Surya TURLAPATI, Mathew GEORGE
  • Publication number: 20220342911
    Abstract: A method for data ingestion for a data visualization platform comprises receiving a plurality of data sets, generating and storing a merged data set based on the plurality of received data sets, and, receiving, via a graphical user interface, a first input comprising an instruction to perform a data standardization operation. The method comprises, in response to receiving the first input, applying a data standardization operation to the merged data set to process the merged data set to generate a standardized data set. The method comprises receiving, via the interface, a second input comprising an instruction to perform a data analytics operation, and responsively applying the data analytics operation to the standardized data set to generate insights data. The method includes receiving, via the interface, a third input comprising an instruction to perform a data visualization operation, and responsively generating one or more data visualizations based on the insights data.
    Type: Application
    Filed: January 19, 2022
    Publication date: October 27, 2022
    Applicant: PricewaterhouseCoopers LLP
    Inventors: Amit DHIR, Pradnesh DESHMUKH, Vasundhara RUNGTA, Pranati DANG, Aparna PRASANNAN, Vishal ADKAR, Mathew GEORGE
  • Publication number: 20220343354
    Abstract: Systems, methods, and graphical user interfaces (GUIs) for visualizing price-book data are provided. Product identifiers and associated price data points are ingested from a plurality of sources and stored in accordance with a product hierarchy. The product identifiers are furthermore organized into a plurality of price books that have a nested relationship with one another. A GUI is provided by which a user may execute an instruction to visualize a portion of the stored data, wherein the input comprises an indication of a subset of the plurality of product identifiers comprising an indication of one or more of the price books. In response to detecting the input, the system generates and displays a visualization based at least in part on the input. Users may further use the GUI to modify one or more price data points in a price book, including simultaneously modifying price data points across multiple price books.
    Type: Application
    Filed: January 19, 2022
    Publication date: October 27, 2022
    Applicant: PricewaterhouseCoopers LLP
    Inventors: Amit DHIR, Giridhar SRINIVASA
  • Patent number: 8180919
    Abstract: According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as a programmable logic device. The use of the soft processor or embedded processors on the device reduces the load on the host processor on the line card. According to some aspects of the invention, the devices takes advantage of an embedded, dedicated processor and/or soft processor(s) to allow for a distributed processing on a single chip.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: May 15, 2012
    Assignee: Xilinx, Inc.
    Inventors: Francis G. Melinn, Amit Dhir
  • Patent number: 7142557
    Abstract: Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: November 28, 2006
    Assignee: Xilinx, Inc.
    Inventors: Amit Dhir, Krishna Rangasayee
  • Patent number: 6957283
    Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: October 18, 2005
    Assignee: Xilinx, Inc.
    Inventors: Amit Dhir, Krishna Rangasayee
  • Publication number: 20050084076
    Abstract: Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.
    Type: Application
    Filed: December 3, 2001
    Publication date: April 21, 2005
    Applicant: Xilinx, Inc.
    Inventors: Amit Dhir, Krishna Rangasayee
  • Publication number: 20030023762
    Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.
    Type: Application
    Filed: July 25, 2001
    Publication date: January 30, 2003
    Applicant: Xilinx, Inc.
    Inventors: Amit Dhir, Krishna Rangasayee