Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Abstract: A three-dimensional puzzle has a monitoring puzzle piece and multiple monitored puzzle pieces. For puzzle pattern determination, the monitoring puzzle piece is equipped with sensors, a processor, a wireless transceiver, and optionally a gyroscope sensor. The monitored puzzle pieces are rotatably connected to each other and to the monitoring puzzle piece to form the puzzle. The sensors, together with the processor or alternatively with an external client, track the monitored puzzle piece rotating relative to the monitoring puzzle piece. The external client may provide feedback to a user of the puzzle. The system enables the competitions between the user and users of other puzzles without requiring the physical proximity of the competitors.

Abstract: Disclosed herein are embodiments of three-dimensional puzzles that implement image sensors to read signatures of individual shell segments to thereby determine shell segment patterns. Also disclosed are embodiments of systems that implement RGB sensors adjacent gradient color maps to provide contactless absolute position encoders.

Abstract: Embodiments disclosed herein include methods and apparatus for tracking three-dimensional puzzle components using embedded signature and rotation sensors. A system of unique signatures enable the identification of the components by internal sensors and rotation sensors enable tracking the components as the move around on the puzzle surface. The system fosters greater enjoyment of the puzzles by offering interactive feedback and guidance. Competitions are also facilitated.

Abstract: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.

Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Abstract: Method, apparatus and system embodiments are disclosed for one or more programmable registers to hold wakeup time values for power management. For at least one embodiment, information based on the values in the programmable registers may be utilized by a power management unit to determine whether a power island has had sufficient time to transition out of a low power state. The values of the programmable registers may be dynamically modified during operation of a processing system. Other embodiments are also described and claimed.

Abstract: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.

Abstract: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.

Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Abstract: Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number.

Abstract: Method, apparatus and system embodiments are disclosed for one or more programmable registers to hold wakeup time values for power management. For at least one embodiment, information based on the values in the programmable registers may be utilized by a power management unit to determine whether a power island has had sufficient time to transition out of a low power state. The values of the programmable registers may be dynamically modified during operation of a processing system. Other embodiments are also described and claimed.

Abstract: An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.

Abstract: A device and method for performing high speed low overhead context switch, and especially in processors that handle multilevel nested tasks. The device handles forward requests and backward requests. The device is coupled to a central processing unit and has plurality of register files and a direct memory access mechanism that allows a processor to respond to a forward request by starting to handle a higher priority task using a first register file while transferring the halted task context from the second register file to a context save area within a memory module. The processor responds to a backward request by using the context that is stored in a first register file, while transferring to the second register file a lower priority task context.