Patents by Inventor Amit Dua

Amit Dua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260342576
    Abstract: Present invention discloses a system and a method for facilitating decentralized identity management. System receive at least one data packet from one or more computing device associated with one or more user. System stores at least one data packet in a decentralized identity network for enabling the one more user to control the identity data. System generates and transmit a zero-knowledge proof corresponding to the at least one data packet to perform an authentication process of the one or more user. System verifies the zero-knowledge proof without accessing the identity data and grant access to a requested service by facilitating decentralized identity management, and enable seamless interoperability between one or more platforms and services upon successful verification.
    Type: Application
    Filed: April 22, 2024
    Publication date: October 29, 2026
    Inventor: Amit DUA
  • Publication number: 20250053431
    Abstract: The invention relates to computer-implemented systems and methods for implementing an automated process and application transformation solution. An embodiment of the present invention is directed to accelerating the digital transformation of legacy applications, e.g., moving older applications to new targeted solutions. An embodiment of the present invention is directed to creating a sequential approach to automating these stages using a combination of technologies and Artificial Intelligence (AI) capabilities. These AI capabilities further augment existing resources and enhance experiences.
    Type: Application
    Filed: August 12, 2024
    Publication date: February 13, 2025
    Inventors: Aaron Purcell, Amit Dua, Hoi-Hung Tsang
  • Patent number: 11429770
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: August 30, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dua, Amit Aggarwal, Manu Chopra, Hemant Gupta, Amit Sharma, Abhishek Raheja
  • Patent number: 10325042
    Abstract: Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 18, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Sharma, Amit Aggarwal, Amit Dua, Manu Chopra, Vincent Reynolds, Abhishek Raheja