Patents by Inventor Amit Gal

Amit Gal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12549454
    Abstract: As described herein, a system, method, and computer program are provided for a TOSCA modeling optimization for 5G network orchestration. A template catalog storing one or more network service instance templates is accessed, by a TOSCA-based orchestrator in a 5G network. A network service instance is deployed to the 5G network from the one or more network service instance templates, by the TOSCA-based orchestrator.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: February 10, 2026
    Assignee: AMDOCS DEVELOPMENT LIMITED
    Inventors: Andrei Kojukhov, Avi Chapnick, Borislav Glozman, Gabriel Podolsky, Amit Gal
  • Publication number: 20240323101
    Abstract: As described herein, a system, method, and computer program are provided for a TOSCA modeling optimization for 5G network orchestration. A template catalog storing one or more network service instance templates is accessed, by a TOSCA-based orchestrator in a 5G network. A network service instance is deployed to the 5G network from the one or more network service instance templates, by the TOSCA-based orchestrator.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Andrei Kojukhov, Avi Chapnick, Borislav Glozman, Gabriel Podolsky, Amit Gal
  • Patent number: 8296697
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 23, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy
  • Patent number: 7870523
    Abstract: The present invention provides a system and method for resolving a test generation problem involving constraint resolution problems where a verification environment includes constraints that are suitable for resolution using one type of solver for a first domain and other constraints that are suitable for resolution using a different solver in a second domain. The invention further comprises variables and, in instances where at least one variable is in each of the first and second domains, using these solvers to restrict the set of permissible values of variables to be consistent in multiple domains, preferably in all relevant domains. A constraint resolution problem is divided into clusters of constraints connected within a domain, and connected clusters of clusters that are connected through shared variables that are subject to constraints in more than one cluster.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 11, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shlomi Uziel, Amos Noy, Vitaly Lagoon, Yael Kinderman, Amit Gal
  • Publication number: 20080235640
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy
  • Publication number: 20020138353
    Abstract: A method for analyzing a plurality of sets of elements, and determining which sets from among the plurality of sets have elements in common with a trial set, including arranging a stored plurality of sets according to a directed graph data structure, the directed graph including nodes that correspond to sets and including directed edges that correspond to a relationship of set-wise inclusion, for a given trial set, denoted T, finding, within the directed graph, a smallest set, denoted S, that contains T, and determining whether T has a non-empty intersection with sets of the directed graph that are contained within S. A system is also described and claimed.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 26, 2002
    Inventors: Zvi Schreiber, Amit Gal