Abstract: A memory component includes a first region of memory cells to store a machine learning model and a second region of the memory cells to store input data and output data of a machine learning operation. The memory component can further include in-memory logic coupled to the first region of the memory cells and the second region of the memory cells via one more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.

Abstract: A system includes a memory component to store host data from a host system and to store a machine learning model and input data. A controller includes an in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and provide the additional host data to the memory component. An additional bus can receive machine learning data from the host system and provide the machine learning data to the in-memory logic that is to perform the machine learning operation.

Abstract: A memory component can include memory cells where a first region of the memory cells is to store a machine learning model and a second region of the memory cells is to store input data and output data of a machine learning operation. A controller can be coupled to the memory component with one more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.

Abstract: Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.

Abstract: A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.

Abstract: A method and system for rendering web content on an end device is disclosed. An encoding server parses the web content to determine a plurality of markup tags in a native markup language associated with the web content. On determining the plurality of markup tags in the native markup language, the encoding server encodes the plurality of markup tags using a rendering markup language to form one or more packages. The rendering markup language defines a set of markup tags in the rendering markup language for each package based on the capabilities and configurations of the end device. The one or more packages are then decoded by a thin client by interpreting the set of markup tags in the rendering markup language. Since the thin client only decodes the set of tags in the rendering markup language, processing power required at the thin client is significantly reduced.

Abstract: Embodiments disclosed herein describe a network device including a class AB common mode suppression (CMS) circuit coupled in parallel between a line voltage source and a physical layer (PHY) device that provides active EMI suppression and Phy device termination. A network connector is coupled to provide the line voltage source to the class AB CMS circuit. The class AB CMS circuit provides current to the PHY device, terminates open-drain transmit drivers of the PHY device and suppresses common mode noise thereby minimizing electromagnetic interference. In other embodiments, the class AB CMS circuit is coupled in parallel between the network connector and a physical layer (PHY) device. The class AB CMS circuit suppresses common mode noise, and terminates open-drain transmit drivers of the PHY device, thereby minimizing electromagnetic interference.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device. First and second resistors are respectively coupled to the differential lines between the integrated active common mode suppression and electrostatic discharge protection circuit and the electronic device.

Abstract: Embodiments disclosed herein describe a network device including a class AB common mode suppression (CMS) circuit coupled in parallel between a line voltage source and a physical layer (PHY) device that provides active EMI suppression and Phy device termination. A network connector is coupled to provide the line voltage source to the class AB CMS circuit. The class AB CMS circuit provides current to the PHY device, terminates open-drain transmit drivers of the PHY device and suppresses common mode noise thereby minimizing electromagnetic interference. In other embodiments, the class AB CMS circuit is coupled in parallel between the network connector and a physical layer (PHY) device. The class AB CMS circuit suppresses common mode noise, and terminates open-drain transmit drivers of the PHY device, thereby minimizing electromagnetic interference.

Abstract: Embodiments disclosed herein provide a network device including an electronic load circuit coupled in parallel between a non-magnetic transformer and a physical layer (PHY) module. Data signals are received via a network connector, and the electronic load circuit is operable to provide DC termination of open-drain (DC common-mode control and current sourcing to) transmit drivers of a physical (PHY) layer module. A common-mode suppression (CMS) circuit can be coupled to positive and negative input signals to the PHY layer module. The CMS circuit is operable to block common-mode noise currents while passing differential mode data signal currents bi-directionally between the network connector and the PHY layer module.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an integrated active common mode suppression and electrostatic discharge protection circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: A network device comprises an interface coupling an electronic device to a differential pair of signal lines, and an active common mode suppression circuit coupled to the interface in parallel to differential signal lines of the electronic device.

Abstract: In a network device, an active Electro-Magnetic Interference (EMI) suppression circuit is coupled in parallel to transmit and receive differential signal lines connecting an Ethernet physical layer (PHY) module and a network connector, actively suppressing EMI in a network communications system that replaces a traditional transformer with an active direct connect interface.

Abstract: In a network device, an interface is coupled between an Ethernet physical layer (PHY) module and a network connector, and comprises at least one pair of pins coupled to output connections of the Ethernet physical layer (PHY), a direct current (DC) blocking capacitor coupled to each pin, and a common-mode suppression amplifier coupled between the paired pins.

Abstract: A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop has loop dynamics that are chosen such that the gain of the positive feedback loop is less than one so that the loop will not oscillate under normal operation after power-up.

Abstract: A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.

Abstract: A method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface. An active continuous time summation circuit is used at the output of the switched-capacitor stage to derive the common mode level that is at the output of the switched-capacitor stage. This derived signal is filtered to remove any noise component remaining in it, and is then used as the reference common mode signal in the continuous time stage. This forces the output common mode, and hence the input common mode of the unity gain amplifier stage, to track the common mode output of the switched-capacitor stage. This adaptive tracking eliminates the common mode interface error, which could be present and could vary from die to die (due to parasitic variations). This technique ensures proper tracking of the DC levels between the negative and the positive terminals of the unity gain amplifier, which is essential for low distortion operation of the amplifier.

Abstract: A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.