Patents by Inventor Amit Gil

Amit Gil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146005
    Abstract: Systems and methods for dynamic lane reallocation based on bandwidth needs are disclosed. In one aspect, dynamic repurposing of low-speed lanes for creation of a high-speed lane on a communication bus is disclosed. The repurposed low-speed lanes may be used to support a symmetrical high-speed link or an asymmetrical high-speed link. Further changes are provided to shield conductors in a cable to assist in preventing crosstalk or unwanted electromagnetic emissions. The addition of such a dynamic high-speed lane may assist in data transfer for data intensive use cases.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Adi Menachem, Lalan Jee Mishra, Amit Gil
  • Publication number: 20230095850
    Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin are disclosed. A communication link between a host and a device may include a clock line, a host to device line, and a device to host line. The host may signal a start or stop condition using the clock line and the device may send an acknowledgment of the host's signaling through the device to host line. Once acknowledgment is made, the host may then signal on the host to device line using a protocol such as SPI.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Kishalay Haldar, Amit Gil
  • Patent number: 11609877
    Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin are disclosed. A communication link between a host and a device may include a clock line, a host to device line, and a device to host line. The host may signal a start or stop condition using the clock line and the device may send an acknowledgment of the host's signaling through the device to host line. Once acknowledgment is made, the host may then signal on the host to device line using a protocol such as SPI.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: March 21, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kishalay Haidar, Amit Gil
  • Patent number: 11287842
    Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Yiftach Benjamini, Amit Gil, Shaul Yohai Yifrach
  • Publication number: 20220019548
    Abstract: Nested commands for a radio frequency front end (RFFE) bus are provided. In particular, timing commands may be nested inside a normal data flow. On receipt of a nested timing command, a slave on the RFFE bus suspends or halts an active command and addresses the timing command. On completion of the timing command, the slave returns to the halted command. By allowing such nested commands, counters in the slave that would otherwise be used to track triggers may be eliminated or reduced and power may be conserved by placing a clock signal associated with the bus into a low power mode.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Inventors: Sharon Graif, Amit Gil, Navdeep Mer, Viney Kumar
  • Patent number: 10963035
    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 30, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, James Lionel Panian, Richard Dominic Wietfeldt, Mohit Kishore Prasad, Amit Gil, Shaul Yohai Yifrach
  • Patent number: 10922252
    Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Publication number: 20200341506
    Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Yiftach Benjamini, Amit Gil, Shaul Yohai Yifrach
  • Patent number: 10795400
    Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 6, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yiftach Benjamini, Amit Gil, Shaul Yohai Yifrach
  • Patent number: 10713199
    Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Amit Gil, Sharon Graif
  • Publication number: 20200192838
    Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Patent number: 10645200
    Abstract: Alternate acknowledgment (ACK) signals in a coalescing Transmission Control Protocol/Internet Protocol (TCP/IP) system are disclosed. In one aspect, a network interface card (NIC) examines packet payloads, and the NIC generates an ACK signal for a sending server before sending a coalesced packet to an internal processor. Further, the NIC may examine incoming packets and send an ACK signal to the internal processor for ACK signals that are received from the sending server before sending the coalesced packet to the internal processor. By extracting and sending the ACK signals before sending the corresponding payloads in the coalesced packet, latency that would otherwise be incurred waiting for the ACK signal is eliminated. Elimination of such latency may improve network performance and may provide power savings.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: May 5, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Amit Gil, Shaul Yohai Yifrach
  • Publication number: 20200089645
    Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 19, 2020
    Inventors: Yiftach Benjamini, Lior Amarilio, Amit Gil, James Lionel Panian, Dafna Shaool
  • Patent number: 10572410
    Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Helena Deirdre O'Shea, Lalan Jee Mishra, Richard Dominic Wietfeldt, Mohit Kishore Prasad, Amit Gil, Gary Chang
  • Publication number: 20190332137
    Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Yiftach Benjamini, Amit Gil, Shaul Yohai Yifrach
  • Patent number: 10437552
    Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Amit Gil, Oded Schnitzer
  • Patent number: 10417161
    Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Helena Deirdre O'Shea, Lalan Jee Mishra, Amit Gil, Gary Chang, Mohit Kishore Prasad, Richard Dominic Wietfeldt, Vinay Jain
  • Patent number: 10419852
    Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Amit Gil, Oded Schnitzer
  • Publication number: 20190236042
    Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.
    Type: Application
    Filed: December 13, 2018
    Publication date: August 1, 2019
    Inventors: Helena Deirdre O'SHEA, Lalan Jee MISHRA, Amit GIL, Gary CHANG, Mohit Kishore Prasad, Richard Dominic WIETFELDT, Vinay JAIN
  • Publication number: 20190227962
    Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.
    Type: Application
    Filed: November 16, 2018
    Publication date: July 25, 2019
    Inventors: Helena Deirdre O'SHEA, Lalan Jee MISHRA, Richard Dominic WIETFELDT, Mohit Kishore PRASAD, Amit GIL, Gary CHANG