Patents by Inventor Amit Gopal M. PUROHIT

Amit Gopal M. PUROHIT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reformatting scan patterns in presence of hold type pipelines
    Patent number: 11694010
    Abstract: A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: July 4, 2023
    Assignee: Synopsys, Inc.
    Inventors: Amit Gopal M. Purohit, Sorin Ioan Popa, Denis Martin, Paras Chhabra
  • Packetized power-on-self-test controller for built-in self-test
    Patent number: 11626178
    Abstract: Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 11, 2023
    Assignee: Synopsys, Inc.
    Inventors: Anubhav Sinha, Ramalingam Kolisetti, Amit Gopal M. Purohit, Sai Manish Rao Marru, Sahil Soni, Salvatore Talluto
  • REFORMATTING SCAN PATTERNS IN PRESENCE OF HOLD TYPE PIPELINES
    Publication number: 20220137126
    Abstract: A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 5, 2022
    Inventors: Amit Gopal M. PUROHIT, Sorin Ioan POPA, Denis MARTIN, Paras CHHABRA
  • PACKETIZED POWER-ON-SELF-TEST CONTROLLER FOR BUILT-IN SELF-TEST
    Publication number: 20220108760
    Abstract: Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 7, 2022
    Inventors: Anubhav SINHA, Ramalingam KOLISETTI, Amit Gopal M. PUROHIT, Sai Manish Rao MARRU, Sahil SONI, Salvatore TALLUTO