Patents by Inventor Amit Gur

Amit Gur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200290102
    Abstract: A medical waste treatment system, comprising: (1) A main treatment unit comprising: a waste receiver cover comprising a UV lamp; a waste shredding unit comprising a shredding bin and at least two rotating shredding blades; a compression unit to push the medical waste towards the shredding blades; a separator to allow the passage of shredded medical waste of a predefined shape and diameter; and a disinfectant delivery unit comprising a plurality of nozzles. (2) A disinfection unit which comprises a disinfectant mixing bin and a mixing unit. (3) A main liquid management unit comprising a disinfectant delivery unit that comprises a plurality of nozzles interconnected to the main treatment unit. (4) A separator unit to separate the liquid from shredded waste; and a centrifuge to further remove liquid from the shredded waste.
    Type: Application
    Filed: November 19, 2018
    Publication date: September 17, 2020
    Inventors: Amit GUR, Amit SHELEG, Mark GERSHKOVICH, Gidi ARNON, Doron EGOZI
  • Publication number: 20190369696
    Abstract: Apparatus, devices, systems, methods, and articles of manufacture are disclosed to allocate power in a computing device. An example system includes a compiler to: analyze power consumption behavior of power consumption units of the computing device; build a power profile; and generate source code with hints of the power profile. The example system includes a power control circuit to: develop a power policy using the hints of the power profile and requests for power licenses from the power consumption units of the computing device; and allocate power to the power consumption units based on the power profile.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: Anat Heilper, Eran Dagan, Amit Bleiweiss, Amit Gur
  • Publication number: 20190011976
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10176560
    Abstract: Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Amit Gur, Rakefet Kol, Edwin Van Dalen, Tamir Klein
  • Publication number: 20180336668
    Abstract: Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Applicant: Intel Corporation
    Inventors: Amit GUR, Rakefet KOL, Edwin VAN DALEN, Tamir KLEIN
  • Patent number: 10114448
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S R Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10037598
    Abstract: Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Amit Gur, Rakefet Kol, Edwin Van Dalen, Tamir Klein
  • Publication number: 20180150943
    Abstract: Techniques related to multi-block memory reads for image de-warping are discussed. Such techniques may include copying pixel data corresponding to overlapping regions of memory between adjacent image modification regions from a local buffer and retrieving pixel data corresponding to non-overlapping regions from external memory.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Amit GUR, Rakefet KOL, Edwin VAN DALEN, Tamir KLEIN
  • Patent number: 9935873
    Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: April 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Roy Shor, Ori Goren, Amit Gur, Gad Yuval
  • Patent number: 9824044
    Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Roy Shor, Nir Baruch, Ori Goren, Amit Gur
  • Publication number: 20160134521
    Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.
    Type: Application
    Filed: June 18, 2013
    Publication date: May 12, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: ROY SHOR, ORI GOREN, AMIT GUR, GAD YUVAL
  • Patent number: 9292456
    Abstract: A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vinay Gupta, Nir Baruch, Amit Gur
  • Publication number: 20160004296
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Intel Corporation
    Inventors: JAWADH HAJ-YIHIA, ELIEZER WEISSMANN, VIJAY S R DEGALAHAL, NADAV SHULMAN, TAL KUZI, ITAY FRANKO, AMIT GUR, EFRAIM ROTEM
  • Publication number: 20150347332
    Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.
    Type: Application
    Filed: January 10, 2013
    Publication date: December 3, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: ROY SHOR, NIR BARUCH, ORI GOREN, AMIT GUR
  • Publication number: 20150081934
    Abstract: A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Inventors: Vinay Gupta, Nir Baruch, Amit Gur
  • Patent number: 8832378
    Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: September 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
  • Patent number: 8103833
    Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: January 24, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shai Koren, Alon Eldar, Amit Gur, Itay Peled, Rotem Porat
  • Patent number: 8006015
    Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Itay Peled
  • Publication number: 20110022800
    Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.
    Type: Application
    Filed: April 11, 2008
    Publication date: January 27, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
  • Publication number: 20100250806
    Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.
    Type: Application
    Filed: November 8, 2006
    Publication date: September 30, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Italy Peled