Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: Dynamic determination of threshold power level for use in distinguishing between downlink and uplink periods in time-division duplexed (TDD) communications. For example, downlink and uplink periods may be distinguished in TDD communications in a distributed communications system (DCS), such as a distributed antenna system (DAS). Detecting a power level in a TDD communications signal less than the threshold power level is used to identify uplink periods in the TDD communications signal. In this manner, TDD communications circuits involved with transmitting TDD communications signals can synchronize their transmission circuitry to only transmit downlink TDD communications signals in downlink periods and receive uplink TDD communications signals in uplink periods.

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Abstract: Dynamic determination of threshold power level for use in distinguishing between downlink and uplink periods in time-division duplexed (TDD) communications. For example, downlink and uplink periods may be distinguished in TDD communications in a distributed communications system (DCS), such as a distributed antenna system (DAS). Detecting a power level in a TDD communications signal less than the threshold power level is used to identify uplink periods in the TDD communications signal. In this manner, TDD communications circuits involved with transmitting TDD communications signals can synchronize their transmission circuitry to only transmit downlink TDD communications signals in downlink periods and receive uplink TDD communications signals in uplink periods.

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Abstract: Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.