Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.