Abstract: A device may receive data associated with one or more healthcare organizations. The data may relate to a performance of one or more processes or operations of the one or more healthcare organizations. The device may process the data using one or more techniques to permit mapping of the data to a healthcare operating model. The device may map the data to the healthcare operating model. The healthcare operating model may be used to perform one or more analyses of the one or more processes or operations of the one or more healthcare organizations. The device may perform one or more analyses of the data to identify one or more deficiencies related to the one or more processes or operations. The device may perform one or more actions to positively impact the performance of the one or more processes or operations of the one or more healthcare organizations.

Abstract: A device may receive first data associated with a set of systems used to implement a process. The device may determine a system topology for the set of systems. The device may identify a set of control points associated with the set of systems. The set of control points may include a set of points in the system topology where second data is received or provided by the set of systems. The second data may include information to be used by the set of systems during the process. The device may identify a set of values for a set of metrics related to the set of systems. The set of values may be identified based on the first data. The device may identify an error related to the set of control points or the set of metrics. The device may perform an action to facilitate fixing of the error.

Abstract: A device may receive first data that identifies operations of an organization. The operations may be associated with a first manner in which the organization stores second data or a second manner in which the organization generates a contract. The device may process the first data to identify the operations of the organization. The device may perform a first analysis of the first data to determine whether the operations of the organization satisfy a set of rules. The set of rules may indicate the first manner in which the organization is to store the second data. The device may perform a second analysis of the second data to identify an error associated with the second data. The device may perform an action to modify the operations of the organization or to facilitate fixing of the error based on a result of the first analysis or the second analysis.

Abstract: A device may receive first data associated with a set of systems used to implement a process. The device may determine a system topology for the set of systems. The device may identify a set of control points associated with the set of systems. The set of control points may include a set of points in the system topology where second data is received or provided by the set of systems. The second data may include information to be used by the set of systems during the process. The device may identify a set of values for a set of metrics related to the set of systems. The set of values may be identified based on the first data. The device may identify an error related to the set of control points or the set of metrics. The device may perform an action to facilitate fixing of the error.

Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.

Abstract: A device may receive first data associated with a set of systems used to implement a process. The device may determine a system topology for the set of systems. The device may identify a set of control points associated with the set of systems. The set of control points may include a set of points in the system topology where second data is received or provided by the set of systems. The second data may include information to be used by the set of systems during the process. The device may identify a set of values for a set of metrics related to the set of systems. The set of values may be identified based on the first data. The device may identify an error related to the set of control points or the set of metrics. The device may perform an action to facilitate fixing of the error.

Abstract: A device may receive first data that identifies operations of an organization. The operations may be associated with a first manner in which the organization stores second data or a second manner in which the organization generates a contract. The device may process the first data to identify the operations of the organization. The device may perform a first analysis of the first data to determine whether the operations of the organization satisfy a set of rules. The set of rules may indicate the first manner in which the organization is to store the second data. The device may perform a second analysis of the second data to identify an error associated with the second data. The device may perform an action to modify the operations of the organization or to facilitate fixing of the error based on a result of the first analysis or the second analysis.

Abstract: A device may receive first data associated with a set of systems used to implement a process. The device may determine a system topology for the set of systems. The device may identify a set of control points associated with the set of systems. The set of control points may include a set of points in the system topology where second data is received or provided by the set of systems. The second data may include information to be used by the set of systems during the process. The device may identify a set of values for a set of metrics related to the set of systems. The set of values may be identified based on the first data. The device may identify an error related to the set of control points or the set of metrics. The device may perform an action to facilitate fixing of the error.

Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.

Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.

Abstract: A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Abstract: A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.

Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.

Abstract: An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.

Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.