Abstract: A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

Abstract: A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.

Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

Abstract: Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.