Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).

Abstract: Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate methods to delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, and is configured to provide a feedback signal to a summing device, which generates a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, receive error coefficients corresponding to the selected unit elements, and adjust the n-bit digital signal based on the received error coefficients.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.

Abstract: The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.