Patents by Inventor Amit Mehrotra

Amit Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10966099
    Abstract: Various communication systems may benefit from determining a venue value index before deploying wireless communication in the area. A method may include identifying the one or more wireless coverage issues within an area. The method may also include receiving data demand information for the area having the identified one or more wireless coverage issues. In addition, the method may include receiving or determining a total cost of ownership. The total cost of ownership may include a cost of fixing the one or more wireless coverage issues within the area. Further, the method may include calculating a venue value index of the area based on at least one of the total cost of ownership, the data demand information, or an average spectrum efficiency. The method may in addition include performing at least one network administrative task based on the venue value index.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 30, 2021
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Ales Vanek, Reinhard Voese, Amit Mehrotra, Jack Zatz, Peter Love, Carl Wijting, Anoop Kulkarni
  • Publication number: 20200213864
    Abstract: Various communication systems may benefit from determining a venue value index before deploying wireless communication in the area. A method may include identifying the one or more wireless coverage issues within an area. The method may also include receiving data demand information for the area having the identified one or more wireless coverage issues. In addition, the in method may include receiving or determining a total cost of ownership. The total cost of ownership may include a cost of fixing the one or more wireless coverage issues within the area. Further, the method may include calculating a venue value index of the area based on at least one of the total cost of ownership, the data demand information, or an average spectrum efficiency. The method may in addition include performing at least one network administrative task based on the venue value index.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 2, 2020
    Inventors: Ales Vanek, Reinhard Voese, Amit Mehrotra, Jack Zatz, Peter Love, Carl Wijting, Anoop Kulkarni
  • Patent number: 10599881
    Abstract: Simulation waveforms representative of simulation progress are generated and outputted for display. A netlist describing a circuit is accessed, and the circuit is simulated over a simulation runtime period. A simulation completion measurement is determined for the simulation runtime period, and a simulation waveform is generated based on the determined simulation completion measurement. Other simulation waveforms can be generated, for instance waveforms representative of a processing resource load over the simulation runtime period. Multiple simulation waveforms can be correlated and displayed in conjunction with each other, for instance in a common waveform interface.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: March 24, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Amit Mehrotra, Francois Le Grix, Paul Estrada
  • Patent number: 8631362
    Abstract: A system and process for utilizing probability distribution information about process parameters to quantify the probability of manufacturing process variation for variants of circuit designs in order to more efficiently analyze and simulate the designs.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 14, 2014
    Assignee: Berkeley Design Automation, Inc.
    Inventors: Amit Mehrotra, Abhishek Somani, Kurt Johnson, Paul Estrada
  • Patent number: 8473533
    Abstract: A system, computer-readable storage medium, and method directly solves non-linear systems that have the HB Jacobian as the coefficient matrix. The direct solve method can be used to efficiently simulate non-linear circuits in RF or microwave applications. Additionally, the direct solve method can be applied to Fourier envelope applications. Furthermore, the direct solve method can be used together with preconditioners to provide a more efficient iterative solve technique.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: June 25, 2013
    Assignee: Berkeley Design Automation, Inc.
    Inventors: Amit Mehrotra, Abhishek Somani
  • Patent number: 7332974
    Abstract: A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: February 19, 2008
    Assignee: Berkeley Design Automation, Inc.
    Inventors: Amit Mehrotra, Amit Narayan
  • Patent number: 7013438
    Abstract: A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a designer performs layout of physical blocks by estimating an area for each block. After connecting the pins of the blocks with no timing constraints, each wire is assigned to a metal layer, based on length. The delay of each wire is minimized by inserting buffers at optimal distances. The blocks are then partitioned into “cores” and “shells.” The shells and cores are synthesized, and then recombined. This procedure greatly reduces the number of design iterations required to complete a design.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: March 14, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alexander Saldanha, Joe Higgins, Amit Mehrotra
  • Patent number: 6167359
    Abstract: A nonlinear analysis for characterizing phase noise and timing jitter in oscillators is disclosed. The method and apparatus utilize a nonlinear differential equation to characterize the phase error of a given oscillator. A precise stochastic characterization of timing jitter and spectral dispersion is also disclosed based on the nonlinear differential equation. Representative time and frequency domain computational techniques are disclosed for characterizing the phase noise and timing jitter of circuits. In addition, a single scalar constant, c, is utilized to describe jitter and spectral spreading in a noisy oscillator.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: December 26, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Alper Demir, Amit Mehrotra, Jaijeet S. Roychowdhury