Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.

Abstract: Multiple read image sensors, and associated methods for the same, are disclosed herein. In one embodiment, a method comprises reading out a reset level from a pixel to a corresponding sample and hold circuit; storing the reset level to a first storage device and to a second storage device of the sample and hold circuit; reading out a signal level from the pixel to the sample and hold circuit; and storing the signal level to a third storage device and to a fourth storage device of the sample and hold circuit. The reset level and the signal level can correspond to a same correlated double sampling of an image data signal captured by the pixel. The method can further include reading out the reset level from the first storage device; reading out the signal level from the third storage device; and recovering a first copy of the image data signal.

Abstract: An image sensor structure has a visible light detection region and an infrared light detection region neighboring the visible light detection region. The image sensor structure includes a semiconductor substrate, photo sensing members, an infrared absorption enhancing member, a color filter and an infrared pass filter. The semiconductor substrate has a front side and a back side opposite to each other. The first photo sensing member is disposed in the front side of the semiconductor substrate. The infrared absorption enhancing member is in the back side of the semiconductor substrate and only in the infrared light detection region. The color filter is over the back side of the semiconductor substrate and in the visible light detection region. The infrared pass filter is over the infrared absorption enhancing member.

Abstract: An image sensor structure has a visible light detection region and an infrared light detection region neighboring the visible light detection region. The image sensor structure includes a semiconductor substrate, photo sensing members, an infrared absorption enhancing member, a color filter and an infrared pass filter. The semiconductor substrate has a front side and a back side opposite to each other. The first photo sensing member is disposed in the front side of the semiconductor substrate. The infrared absorption enhancing member is in the back side of the semiconductor substrate and only in the infrared light detection region. The color filter is over the back side of the semiconductor substrate and in the visible light detection region. The infrared pass filter is over the infrared absorption enhancing member.

Abstract: A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.

Abstract: An image sensor is provided, wherein the image sensor includes a pixel array and a timing controller coupled to the pixel array. The pixel array includes a plurality of pixel circuits, and each pixel circuit of pixel circuits includes a photodiode and a storage node. The timing controller includes a logic circuit for generating a plurality of control signals to respectively control operations of the pixel circuits within the pixel array. Respective photodiodes of the pixel circuits are concurrently reset to a first reference level before generating respective photodiode signals of the pixel circuits. Respective storage nodes of the pixel circuits are sequentially reset to a second reference level. The respective photodiode signals of the pixel circuits are concurrently transmitted to the respective storage nodes of the pixel circuits. The respective photodiode signals of the pixel circuits are sequentially read out from the respective storage nodes of the pixel circuits.

Abstract: An image capturing device including an image sensing circuit and a processing circuit is provided. The processing circuit controls the image sensing circuit to sense at least one partial frame before sensing a full frame. A number of pixels of the partial frame is less than a number of pixels of the full frame, and exposure time of the partial frame is shorter than exposure time of the full frame. The processing circuit performs an automatic exposure procedure according to the partial frame to calculate a fast exposure time and gain, transforms the fast exposure time and gain into exposure time and gain for the full fame, and control the image sensing circuit to sense the full frame accordingly.

Abstract: A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.

Abstract: A camera system is provided and includes a processor, a first camera, a second camera, and a data bus. The processor transmits a first trigger signal to the first camera to enable the first camera outputting first data to the processor through the data bus. The first camera transmits a second trigger signal to the second camera to enable the second camera outputting second data to the processor through the data bus.

Abstract: An anti-eclipse circuit for use in an imager includes a differential amplifier and a feedback circuit. The differential amplifier is coupled to an output line for receiving an output signal associated with the voltage level of a floating diffusion region in a pixel of the imager and configured to detect when a reset signal received from the pixel drops below a predetermined level. The feedback circuit is configured to increase the reset signal when the output signal is lower than the clamp voltage, thereby keeping the reset signal at the constant level.

Abstract: The invention is directed to a method of operating an image sensor. A first integration is performed on a first photodiode of a pixel circuit to obtain at least one first image signal. A second integration is performed on a second photodiode of the pixel circuit to obtain a second image signal, the first photodiode having a photodiode area larger than the second photodiode. A third integration is performed by collecting blooming charge overflowing from the first photodiode to obtain an overflow image signal. The first integration has longest integration time and the third integration has shortest integration time among the first integration, the second integration and the third integration.

Abstract: The invention is directed to a method of operating an image sensor. A first integration is performed on a first photodiode of a pixel circuit to obtain at least one first image signal. A second integration is performed on a second photodiode of the pixel circuit to obtain a second image signal, the first photodiode having a photodiode area larger than the second photodiode. A third integration is performed by collecting blooming charge overflowing from the first photodiode to obtain an overflow image signal. The first integration has longest integration time and the third integration has shortest integration time among the first integration, the second integration and the third integration.

Abstract: An analog block implemented with a band-gap reference scheme for use in a device includes a mode control unit and a band-gap reference circuit. The mode control unit is configured to generate a mode selection signal associated with the operational mode of the device. The band-gap reference circuit includes a bias generator, an error amplifier, and a band-gap loop circuit. The bias generator is configured to provide a band-gap reference voltage in a first bias state when the device operates in a normal mode or in a second bias state when the device operates in a standby mode. The error amplifier is configured to generate an error voltage according to the bias voltage. The band-gap loop circuit is configured to provide a band-gap reference voltage according to the error voltage. First current flowing through the bias generator in the first bias state is larger than second current flowing through the bias generator in the second bias state.

Abstract: An anti-eclipse circuit for use in an imager includes a differential amplifier and a feedback circuit. The differential amplifier is coupled to an output line for receiving an output signal associated with the voltage level of a floating diffusion region in a pixel of the imager and configured to detect when a reset signal received from the pixel drops below a predetermined level. The feedback circuit is configured to increase the reset signal when the output signal is lower than the clamp voltage, thereby keeping the reset signal at the constant level.

Abstract: A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.

Abstract: An image sensor includes readout circuits coupled to read out integrated light signals from pixels via bitlines respectively. Each readout circuit includes a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC). At least two pixels of a row share a bitline and an associated readout circuit. The ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other.

Abstract: An image sensor includes readout circuits coupled to read out integrated light signals from pixels via bitlines respectively. Each readout circuit includes a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC). At least two pixels of a row share a bitline and an associated readout circuit. The ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other.

Abstract: A method of adaptively reducing power consumption in an image sensor includes using an electronic rolling shutter to reset pixels of the image sensor row by row. Signal charges are read out from the pixels row by row, followed by obtaining an integration time and a frame height. A power-saving signal is generated when the integration time is substantially greater than the frame height, and at least a circuitry that is not required to operate during an active period of the power-saving signal is turned off.