Patents by Inventor Amit Nahar

Amit Nahar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11686764
    Abstract: An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 27, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sirish Boddikurapati, Amit Nahar
  • Publication number: 20210181253
    Abstract: A method for failed die clustering is provided that includes extracting a data set of failed die on a wafer from a wafer map for the wafer, determining a density parameter for clustering the failed die, removing false failures from the data set of failed die to generate a reduced data set of failed die, locating clusters of failed die in the reduced data set by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and applying a guard band to each located cluster.
    Type: Application
    Filed: November 12, 2020
    Publication date: June 17, 2021
    Inventors: Istvan Bauer, Michael Menne Haggerty, Scott Eric Riddle, Peter W. Kinghorn, Amit Nahar, Glenn Edward Schuette, Russell K. Kneupper
  • Publication number: 20210063479
    Abstract: An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.
    Type: Application
    Filed: August 24, 2020
    Publication date: March 4, 2021
    Inventors: Sirish Boddikurapati, Amit Nahar