Patents by Inventor Amit P. Agrawal

Amit P. Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High data rate differential signal line design for uniform characteristic impedance for high performance integrated circuit packages
    Patent number: 7013437
    Abstract: Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal escaping portion and a remaining portion. The apparatus also includes differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments. The first segment extends through the escaping portion and the second segment extends through the remaining portion. The first and second segments have respective first and second widths.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: March 14, 2006
    Assignee: Broadcom Corporation
    Inventor: Amit P. Agrawal
  • High data rate differential signal line design for uniform characteristic impedance for high performance integrated circuit packages
    Publication number: 20040268271
    Abstract: Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal escaping portion and a remaining portion. The apparatus also includes differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments. The first segment extends through the escaping portion and the second segment extends through the remaining portion. The first and second segments have respective first and second widths.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Inventor: Amit P. Agrawal
  • Testable low inductance integrated circuit package
    Patent number: 6034426
    Abstract: A low inductance integrated circuit package such as a ball grid array having mounting conductors formed on a first side thereof and a die attachment region formed on second side thereof. A plurality of conductors internal to the package interconnect the mounting conductors to the die attachment region. A plurality of diagnostic contact pads are connected to the conductors and configured for ready access by a test probe. The contact pads are preferably provided at a periphery of the package.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: March 7, 2000
    Assignee: Hewlett-Packard Co.
    Inventors: Mukesh P. Patel, Amit P. Agrawal