Abstract: A computing system includes a first processing node having one or more processors and a cache subsystem, and a probe filter directory having entries for tracking a plurality of memory locations wherein data stored at the plurality of memory locations are cached in the cache subsystem, the probe filter directory including a first entry for tracking a first memory location of the plurality of memory locations, the first entry taking up a first number of bits, and a second entry for tracking a second memory location of the plurality of memory locations, the second entry taking up a second number of bits, wherein the first number is larger than the second number. Various other methods and systems are also disclosed.

Abstract: A computing system includes a processing node having one or more processors and a cache subsystem, and a region-based probe filter directory having a first and second entry, the first entry containing information of a region of a memory, the second entry containing information of a line in the region of the memory, data stored in the region being cached in the cache subsystem. Various other methods and systems are also disclosed.

Abstract: A computing system includes a first and second processing nodes each including one or more processors and a cache subsystem, and a probe filter directory having a directory entry for tracking cached data from a region of the memory, and a probe filter controller configured to automatically evict the first processing node from the directory entry in order to track the second processing node in the directory entry in response to the second processing node accessing the cached data, wherein the directory entry tracks only one processing node at a time. Various other methods and systems are also disclosed.

Abstract: The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method can include detecting, by at least one processor, a cache load from a second central processing unit (CPU) cache hierarchy onto an exclusively owned cache region of cache memory that is exclusively owned by a first CPU cache hierarchy. The method can additionally include converting, by the at least one processor, the exclusively owned cache region, in response to the detection, to a dual owner cache region at least in part by partitioning one or more fields of an entry for the dual owner cache region in a region-based probe filter. The method can also include employing, by the at least one processor, the entry for the dual owner cache region to track cache subregion subscriptions of both the first CPU cache hierarchy and the second CPU cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

Abstract: The disclosed computer-implemented method can include detecting, by at least one processor, a cache load from a second central processing unit (CPU) cache hierarchy onto an exclusively owned cache region of cache memory that is exclusively owned by a first CPU cache hierarchy. The method can additionally include converting, by the at least one processor, the exclusively owned cache region, in response to the detection, to a dual owner cache region at least in part by partitioning one or more fields of an entry for the dual owner cache region in a region-based probe filter. The method can also include employing, by the at least one processor, the entry for the dual owner cache region to track cache subregion subscriptions of both the first CPU cache hierarchy and the second CPU cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed method can include (i) detecting, by a probe filter in a coherent fabric interconnect, an access request to a specific memory address of a cache hierarchy using a new encryption key, (ii) verifying, by the probe filter, that the specific memory address stores data encrypted using a previous and distinct encryption key, and (iii) evicting, by the probe filter in response to the verifying, references to the previous and distinct encryption key from the cache hierarchy. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computing device includes detection circuitry configured to detect invalidation of a line of a cache array. The computing device additionally includes setting circuitry configured to set, in response to the detected invalidation, a spare state encoding in an entry of a partial line-based probe filter that indicates recent invalidation of the line of the cache array. The computing device also includes processing circuitry configured to process a transaction that hits on the entry of the partial line-based probe filter by avoiding a multicast probe of the cache array. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

Abstract: A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a plurality of entries that store information about each entry. The directory cleaner periodically scans the probe filter and selectively removes a first entry from the probe filter after the first entry is scanned.

Abstract: A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If the entry exists in the cache directory, is invalid, and includes an indication that data corresponding to the memory address includes zero data, the coherency management device returns zero data in response to the request without fetching the data from main memory or a cache.

Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computing device can include at least one memory of a particular type having a plurality of memory channels, and at least one memory of at least one other type having a plurality of links. The computing device can also include remapping circuitry configured to homogenously interleave the plurality of memory channels with the at least one memory of the at least one other type. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.