Abstract: According to one exemplary embodiment, a method for establishing a relationship between Joule heating in a conductor and a current density in the conductor is implemented by performing wafer level measurements. According to this exemplary embodiment, wafer level measurements are performed to arrive at a temperature coefficient of resistance in the conductor. The method also includes determining a thermal resistance of the conductor. The thermal resistance is then utilized to establish a relationship between Joule heating in the conductor and the current density in the conductor. The relationship so obtained is then utilized to determine design rules, mean time to fail, and other information to aid in the design of reliable semiconductor devices. According to another exemplary embodiment, a wafer level measurement system is utilized to establish a relationship between Joule heating in a conductor and a current density in the conductor.

Abstract: For determining electromigration permeability of a layer material, a test line, a feeder line, and a cathode line of an interconnect test structure are formed with current flowing from the test line through the feeder line to the cathode line. A no-flux structure is disposed between the cathode line and the feeder line, and the layer material is disposed between the feeder line and the test line. A respective current density and length product of the feeder line and the test line is respectively less than and greater than a respective critical Blech length constant. An occurrence of a void within the feeder line or the test line indicates that the layer material is permeable or impermeable.

Abstract: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

Abstract: The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.

Abstract: According to one exemplary embodiment, a method for establishing a relationship between Joule heating in a conductor and a current density in the conductor is implemented by performing wafer level measurements. According to this exemplary embodiment, wafer level measurements are performed to arrive at a temperature coefficient of resistance in the conductor. The method also includes determining a thermal resistance of the conductor. The thermal resistance is then utilized to establish a relationship between Joule heating in the conductor and the current density in the conductor. The relationship so obtained is then utilized to determine design rules, mean time to fail, and other information to aid in the design of reliable semiconductor devices. According to another exemplary embodiment, a wafer level measurement system is utilized to establish a relationship between Joule heating in a conductor and a current density in the conductor.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.

Abstract: The introduction of alloying elements into a metal conductive element is achieved in situ in conjunction with a post-CMP reducing treatment. The source of the alloying elements may be a source gas introduced into the plasma chamber, or a source material incorporated into a post-CMP residue through presence in a CMP slurry or a post-CMP rinsing agent, or applied to the substrate prior to plasma treatment. The alloying element is introduced into the metal conductive element by diffusion during plasma treatment.

Abstract: The reliability and electromigration performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor substrate, are enhanced by a method for more reliably and uniformly diffusing into a conductive fill alloying elements which reduce or substantially prevent electromigration. The method comprises depositing around a conductive fill metal alloy films and alloying layers comprising one or more alloying elements having physical and/or chemical attributes which are effective for minimizing or substantially preventing electromigration along grain boundaries and/or along the interface between the surfaces of the conductive fill and other surfaces. The metal alloy films and alloying layers are advantageously deposited where their particular physical and/or chemical attributes may be most beneficial for improving electromigration performance.

Abstract: A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A plurality of consumable remote secondary anodes at different voltages in the plating solution reservoir provides the metal ions for alloy plating.

Abstract: A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.

Abstract: An integrated circuit test system and method therefor is provided having a semiconductor substrate with an electrical ground and a source of electrical potential. A dielectric layer with first and second openings is formed on the semiconductor substrate. First and second barrier layers are deposited on the dielectric layer to line the openings. A first conductor core is deposited over the first barrier layer to fill the first opening and is connected to a source of electrical potential. A second conductor core is deposited over the second barrier layer to fill the second opening and is connected to the electrical ground. A current measuring device is provided to measure leakage current flow between the first and second conductor cores.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has an opening formed therein. A first barrier layer is deposited over the first conductor core. A second barrier layer is deposited to line the low dielectric constant dielectric layer and the first barrier layer. A third barrier layer is deposited to line the second barrier layer. A second conductor core is deposited to fill the opening over the third barrier layer.

Abstract: A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a first conductor core. A via dielectric layer having a via opening which is open to the first conductor core is formed over the first channel dielectric layer. A second channel dielectric layer with a second opening which is open to the via is formed over the via dielectric layer. A second conductor core fills the via and second channel openings. A second barrier layer lining the via and second channel openings under the second conductor core forms a barrier between the second conductor core and the via and second channel dielectric layers, but does not form a barrier between the first and the second conductor cores.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.