Patents by Inventor Amit Rane

Amit Rane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11743080
    Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Amit Rane, Ashwin Kottilvalappil Vijayan
  • Publication number: 20230246884
    Abstract: Systems, circuitry and methods correct baseline wander while reducing amplitude difference between the input signal to a data sampler and the output signal of an output-swing-controlled buffer. Example baseline wander correction circuitry comprises a baseline wander correction loop that receives an equalized data signal, a feedback signal and a buffer control signal, and corrects baseline wander in the data sampler input signal. Baseline wander correction loop generates the buffer output signal based on the data sampler output signal and the buffer control signal. Baseline wander correction circuitry also comprises a feedback circuit that receives the data sampler output signal and generates the feedback signal, and an amplitude estimation loop that receives the data sampler input and output signals and outputs the buffer control signal to control the peak-to-peak swing of the buffer output signal.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Inventors: Abishek Manian, Amit Rane
  • Patent number: 11539555
    Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Ashwin Kottilvalappil Vijayan, Amit Rane, Ashkan Roshan Zamir
  • Patent number: 11356086
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Amit Rane
  • Publication number: 20210409246
    Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.
    Type: Application
    Filed: November 12, 2020
    Publication date: December 30, 2021
    Inventors: Abishek MANIAN, Ashwin Kottilvalappil VIJAYAN, Amit RANE, Ashkan ROSHAN ZAMIR
  • Publication number: 20210409248
    Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.
    Type: Application
    Filed: October 28, 2020
    Publication date: December 30, 2021
    Inventors: Abishek MANIAN, Amit RANE, Ashwin Kottilvalappil VIJAYAN
  • Patent number: 11038723
    Abstract: At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 15, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Rane, Charles Michael Campbell, Suzanne Mary Vining
  • Publication number: 20210159896
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Huanzhang HUANG, Amit RANE
  • Patent number: 10979252
    Abstract: Aspects of the disclosure provide for a circuit comprising a transmitter. In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path to generate the output signal when the loss of signal indication signal has a second value.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yanli Fan, Amit Rane
  • Patent number: 10972319
    Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 6, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amit Rane
  • Publication number: 20210075650
    Abstract: At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.
    Type: Application
    Filed: January 31, 2020
    Publication date: March 11, 2021
    Inventors: Amit RANE, Charles Michael CAMPBELL, Suzanne Mary VINING
  • Patent number: 10938385
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Amit Rane
  • Publication number: 20200350899
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 5, 2020
    Inventors: Huanzhang HUANG, Amit RANE
  • Patent number: 10804956
    Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Amit Rane
  • Patent number: 10763841
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Amit Rane
  • Patent number: 10749716
    Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dongwei Chen, Amit Rane
  • Publication number: 20200084069
    Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventor: Amit RANE
  • Publication number: 20200052684
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 13, 2020
    Inventors: Huanzhang HUANG, Amit RANE
  • Publication number: 20200044686
    Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Abishek MANIAN, Amit RANE
  • Patent number: 10484042
    Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Amit Rane