Patents by Inventor Amit Rane
Amit Rane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11743080Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.Type: GrantFiled: October 28, 2020Date of Patent: August 29, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Amit Rane, Ashwin Kottilvalappil Vijayan
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Publication number: 20230246884Abstract: Systems, circuitry and methods correct baseline wander while reducing amplitude difference between the input signal to a data sampler and the output signal of an output-swing-controlled buffer. Example baseline wander correction circuitry comprises a baseline wander correction loop that receives an equalized data signal, a feedback signal and a buffer control signal, and corrects baseline wander in the data sampler input signal. Baseline wander correction loop generates the buffer output signal based on the data sampler output signal and the buffer control signal. Baseline wander correction circuitry also comprises a feedback circuit that receives the data sampler output signal and generates the feedback signal, and an amplitude estimation loop that receives the data sampler input and output signals and outputs the buffer control signal to control the peak-to-peak swing of the buffer output signal.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Abishek Manian, Amit Rane
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Patent number: 11539555Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.Type: GrantFiled: November 12, 2020Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Ashwin Kottilvalappil Vijayan, Amit Rane, Ashkan Roshan Zamir
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Patent number: 11356086Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: GrantFiled: February 1, 2021Date of Patent: June 7, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huanzhang Huang, Amit Rane
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Publication number: 20210409246Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.Type: ApplicationFiled: November 12, 2020Publication date: December 30, 2021Inventors: Abishek MANIAN, Ashwin Kottilvalappil VIJAYAN, Amit RANE, Ashkan ROSHAN ZAMIR
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Publication number: 20210409248Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.Type: ApplicationFiled: October 28, 2020Publication date: December 30, 2021Inventors: Abishek MANIAN, Amit RANE, Ashwin Kottilvalappil VIJAYAN
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Patent number: 11038723Abstract: At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.Type: GrantFiled: January 31, 2020Date of Patent: June 15, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Rane, Charles Michael Campbell, Suzanne Mary Vining
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Publication number: 20210159896Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: Huanzhang HUANG, Amit RANE
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Patent number: 10979252Abstract: Aspects of the disclosure provide for a circuit comprising a transmitter. In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path to generate the output signal when the loss of signal indication signal has a second value.Type: GrantFiled: June 4, 2020Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yanli Fan, Amit Rane
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Patent number: 10972319Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.Type: GrantFiled: September 12, 2018Date of Patent: April 6, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Amit Rane
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Publication number: 20210075650Abstract: At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.Type: ApplicationFiled: January 31, 2020Publication date: March 11, 2021Inventors: Amit RANE, Charles Michael CAMPBELL, Suzanne Mary VINING
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Patent number: 10938385Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: GrantFiled: July 23, 2020Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huanzhang Huang, Amit Rane
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Publication number: 20200350899Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: ApplicationFiled: July 23, 2020Publication date: November 5, 2020Inventors: Huanzhang HUANG, Amit RANE
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Patent number: 10804956Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.Type: GrantFiled: October 11, 2019Date of Patent: October 13, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Amit Rane
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Patent number: 10763841Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: GrantFiled: August 8, 2019Date of Patent: September 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Huanzhang Huang, Amit Rane
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Patent number: 10749716Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).Type: GrantFiled: April 23, 2018Date of Patent: August 18, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dongwei Chen, Amit Rane
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Publication number: 20200084069Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Inventor: Amit RANE
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Publication number: 20200052684Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.Type: ApplicationFiled: August 8, 2019Publication date: February 13, 2020Inventors: Huanzhang HUANG, Amit RANE
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Publication number: 20200044686Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Abishek MANIAN, Amit RANE
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Patent number: 10484042Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.Type: GrantFiled: August 31, 2018Date of Patent: November 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Amit Rane