Patents by Inventor Amit Roy

Amit Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190179941
    Abstract: There is provided a method including determining whether a selection of database query identifiers is to be made in a fixed manner or a dynamic manner. The method also includes generating a collection including the selection from a list including database query identifiers related to a database. When the selection is to be made in the fixed manner, the selection of the database query identifiers includes a view name and/or database query logic. When the selection is to be made in the dynamic manner, the selection of the database query identifiers includes a corresponding view name. The method also includes generating a materialized view corresponding to a given database query identifier in the collection. Moreover, the method includes storing an identifier of the materialized view in association with the given database query identifier.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventors: Kevin Williams, Amit Kumar Singh, Gaurav Roy
  • Publication number: 20190179929
    Abstract: A system is provided including a memory in communication with a processor. The memory stores data including an entity value of an entity stored in association with an attribute value of an attribute of the entity. The processor stores an entity value identifier in association with an attribute value identifier to obtain modified data. The entity value identifier is associated with the entity value and the attribute value identifier is associated with the attribute value. The processor also transforms the modified data by applying a transformation to the modified data to obtain transformed data. In addition, the processor outputs further modified data from the transformed data, the further modified data including the transformed data with the entity value identifier replaced with the entity value and the attribute value identifier replaced with the attribute value.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Kevin Williams, Amit Kumar Singh, Gaurav Roy
  • Patent number: 9294078
    Abstract: A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 22, 2016
    Assignee: REESCALE SEMICONDUCTOR,INC.
    Inventors: Chetan Verma, Geetansh Arora, Amit Roy
  • Patent number: 9292651
    Abstract: A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chetan Verma, Amit Kumar Dey, Ashis Maitra, Kulbhushan Misri, Amit Roy, Harkaran Singh, Vijay Tayal
  • Publication number: 20160072488
    Abstract: A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 10, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Geetansh Arora, Amit Roy
  • Publication number: 20150316950
    Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 5, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Kumar Dey, Himanshu Mangal, Kulbhushan Misri, Amit Roy, Vijay Tayal, Chetan Verma
  • Patent number: 9176522
    Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 3, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Kumar Dey, Himanshu Mangal, Kulbhushan Misri, Amit Roy, Vijay Tayal, Chetan Verma
  • Patent number: 9166585
    Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 20, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
  • Publication number: 20150248519
    Abstract: A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Inventors: Chetan Verma, Amit Kumar Dey, Ashis Maitra, Kulbhushan Misri, Amit Roy, Harkaran Singh, Vijay Tayal
  • Publication number: 20150102839
    Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
    Type: Application
    Filed: August 20, 2014
    Publication date: April 16, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amit Roy, Zhihong Cheng, Amit Kumar Dey, Vijay Tayal, Chetan Verma
  • Patent number: 9003351
    Abstract: A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Kushagra Khorwal, Amit Roy, Rounak Roy, Vijay Tayal
  • Publication number: 20150079100
    Abstract: In certain embodiments, the present invention, the present invention provides a method of treating a cancer in a subject, comprising: (a) administering to the subject a predetermined dosage of an anti-CTLA4 antibody; (b) detecting the level of the anti-CTLA4 antibody in a sample of the subject; and (c) increasing the dosage of the anti-CTLA4 antibody in the subject if the level of the anti-CTLA4 antibody from step (b) is below a threshold exposure level, such that the cancer is treated.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 19, 2015
    Inventors: Amit Roy, Yan Feng, Bruce C. Stouffer
  • Patent number: 8887120
    Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Amit Kumar Dey, Amit Roy, Vijay Tayal
  • Patent number: 8803591
    Abstract: Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Roy, Amit Kumar Dey, Kulbhushan Misri, Vijay Tayal, Chetan Verma
  • Patent number: 8793641
    Abstract: A system and method for determining power leakage of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool that includes a processor and an automatic test pattern generation (ATPG) tool for generating multiple sets of input value strings. The ATPG tool generates test patterns that include input value strings for simulating each digital logic element of the circuit design independently. A mapping between generated output values and corresponding input values is stored in a look up table (LUT). Thereafter, the ATPG tool generates test patterns that include input value strings for simulating the real-time behavior of the circuit design. The processor determines power leakage of the circuit design based on probability of occurrence of each unique input value string at the input of each digital logic element and corresponding predetermined power leakage values.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Roy, Shyam S. Gupta, Nipun Mahajan, Vijay Tayal, Chetan Verma
  • Patent number: 8762922
    Abstract: A system for reducing leakage power of an electronic circuit design, where the circuit design includes multiple timing paths, each timing path made up of multiple cells, using an electronic design automation (EDA) tool. The EDA tool includes a processor that chooses a first replacement cell for replacing a first cell in a first timing path when timing slack is not available in the first path, where a width and threshold voltage of the first replacement cell are greater than a width and threshold voltage of the first cell. The processor then replaces the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than that of the first cell, and when the timing slack is available for replacing the first cell with the first replacement cell.
    Type: Grant
    Filed: October 13, 2013
    Date of Patent: June 24, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Roy, Vijay Tayal, Chetan Verma
  • Patent number: 8527935
    Abstract: A method and system for reducing power consumption of an electronic circuit design using an EDA tool includes generating a look-up table (LUT) that stores a mapping between a type, a predetermined optimum power input transition time, and at least one characteristic corresponding to each digital logic element present in a cell library of the EDA tool. An input transition time of a first digital logic element is determined. Then, the first logic element is replaced with a second logic element if the input transition time and the predetermined optimum power input transition time of the first logic element are not equal. The second logic element may be replaced with a third logic element if a timing delay of the second logic element is greater than a timing delay of the first logic element.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: September 3, 2013
    Assignee: Freescale Semiconductor, Inc
    Inventors: Chetan Verma, Amit Roy, Vijay Tayal
  • Patent number: 8458210
    Abstract: A computing cluster may include servers that connect database servers. In one implementation, a server may receive a resource request from a client and extract a session identifier from the resource request. The server may determine, based on the session identifier, one of the database servers to use in fulfilling the resource request.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: June 4, 2013
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Syed Arifuddin, Amit Roy, Venugopal Jagannathan
  • Publication number: 20120284296
    Abstract: A computing cluster may include servers that connect database servers. In one implementation, a server may receive a resource request from a client and extract a session identifier from the resource request. The server may determine, based on the session identifier, one of the database servers to use in fulfilling the resource request.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 8, 2012
    Applicant: Verizon Patent and Licensing Inc.
    Inventors: Syed Arifuddin, Amit Roy, Venugopal Jagannanthan
  • Publication number: 20100133298
    Abstract: Disclosed is an apparatus comprising a cooling device for at least one bag-in-box package, a feed hole for the bag-in-box package, at least one device door that closes the feed hole, and at least one beverage outlet which can be associated with the tapping valve of the bag-in-box package. The beverage outlet is disposed within the device door.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 3, 2010
    Inventors: Rainer Samson, Amit Roy