Patents by Inventor Amit Sureshkumar Nangia
Amit Sureshkumar Nangia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869820Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: GrantFiled: July 1, 2022Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20230102688Abstract: In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.Type: ApplicationFiled: September 28, 2021Publication date: March 30, 2023Inventors: Amit Sureshkumar Nangia, Gregory Thomas Ostrowicki
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Publication number: 20220415824Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
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Publication number: 20220336304Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Patent number: 11430747Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.Type: GrantFiled: March 4, 2021Date of Patent: August 30, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
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Publication number: 20220246489Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
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Patent number: 11387155Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: GrantFiled: April 27, 2020Date of Patent: July 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20220208695Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.Type: ApplicationFiled: March 4, 2021Publication date: June 30, 2022Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
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Patent number: 11139178Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: GrantFiled: October 15, 2019Date of Patent: October 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Publication number: 20210296196Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
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Patent number: 11121049Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: GrantFiled: January 16, 2019Date of Patent: September 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
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Publication number: 20210183717Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: ApplicationFiled: April 27, 2020Publication date: June 17, 2021Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20200043753Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Inventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Patent number: 10446414Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: GrantFiled: December 22, 2017Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
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Publication number: 20190198352Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Amit Sureshkumar NANGIA, Siva Prakash GURRUM, Janakiraman SEETHARAMAN
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Publication number: 20190172766Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: ApplicationFiled: January 16, 2019Publication date: June 6, 2019Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
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Patent number: 10204842Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: GrantFiled: February 14, 2018Date of Patent: February 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
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Publication number: 20180233422Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.Type: ApplicationFiled: February 14, 2018Publication date: August 16, 2018Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
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Patent number: 9646950Abstract: A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.Type: GrantFiled: February 2, 2016Date of Patent: May 9, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kejun Zeng, Amit Sureshkumar Nangia
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Publication number: 20160181225Abstract: A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.Type: ApplicationFiled: February 2, 2016Publication date: June 23, 2016Inventors: Kejun Zeng, Amit Sureshkumar Nangia