Abstract: A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.

Abstract: A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device .

Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.