Patents by Inventor Amit V Nahar

Amit V Nahar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor outlier identification using serially-combined data transform processing methodologies
    Patent number: 8126681
    Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: February 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Amit V Nahar, John M Carulli, Kenneth M Butler, Thomas J Anderson, Suresh Subramaniam
  • SEMICONDUCTOR OUTLIER IDENTIFICATION USING SERIALLY-COMBINED DATA TRANSFORM PROCESSING METHODOLOGIES
    Publication number: 20110071782
    Abstract: A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.
    Type: Application
    Filed: September 24, 2009
    Publication date: March 24, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AMIT V. NAHAR, JOHN M. CARULLI, JR., KENNETH M. BUTLER, THOMAS J. ANDERSON, SURESH SUBRAMANIAM