Patents by Inventor Amit Vyas

Amit Vyas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11775457
    Abstract: In one example, a command pattern sequencer includes a set of registers to store values used to configure a command sequence for configuring a memory. The command pattern sequencer further includes state machine circuitry coupled to the set of registers, the state machine circuitry configured to generate and execute the command sequence. The command pattern sequencer still further includes timing circuitry configured to manage timing between commands of the command sequence.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: October 3, 2023
    Assignee: XILINX, INC.
    Inventors: Amit Vyas, Ramakrishna Reddy Gaddam, Karthikeyan Palanisamy
  • Patent number: 11152051
    Abstract: A method includes receiving a first and a second data from a first and second IO pad on a first and second data lines respectively. A data strobe is received from a third IO pad on a data strobe line. The first data and the second data are strobed based on the data strobe to generate a first and second strobed data. The first data from the first IO is received at the data strobe line and strobed based on the data strobe to form an another first strobed data and compared to the first strobed data to generate a comparison signal indicating whether adjustment to a delay of the first data line is needed. A delay command is generated to increase/decrease the delay of the first and second data line.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 19, 2021
    Assignee: XILINX, INC.
    Inventors: Amit Vyas, Ramakrishna Reddy Gaddam, Karthikeyan Palanisamy
  • Patent number: 10628065
    Abstract: Some examples of the present disclosure generally relate to integrated circuits that include hardware logic for detecting an edge of a signal. In some examples, an integrated circuit includes a traffic generator, a memory communication path, a comparator, and edge detection hardware logic. The traffic generator, comparator, and edge detection hardware logic are configurable based on a calibration stage. The traffic generator is operable to generate commands to memory via a memory communication path. The comparator is operable to compare data from the memory communication path with known data and to responsively output a comparison status. The data from the memory communication path is in response to the commands generated by the traffic generator. The edge detection hardware logic is operable to detect an edge of a signal based on the comparison status.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Amit Vyas, Ramakrishna R. Gaddam