Patents by Inventor Amitabh Menon
Amitabh Menon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11366783Abstract: An integrated circuit includes a plurality of configurable units, each configurable unit having two or more corresponding sections. The plurality of configurable units is arranged in a serial arrangement to form a chain of sections of the configurable units. A data bus is connected to the plurality of configurable units which communicates data at a clock rate. The chain of sections is to receive and write a series of tensors at the clock rate at a first end section of the chain of sections, and sequentially propagate the series of tensors through individual sections within the chain of sections at the clock rate. The chain of sections is to output the series of tensors at a second end section of the chain of sections. The chain of sections is to also output the series of tensors at an intermediate section of the chain of sections.Type: GrantFiled: March 29, 2021Date of Patent: June 21, 2022Assignee: SambaNova Systems, Inc.Inventors: Raghu Prabhakar, Nathan Francis Sheeley, Amitabh Menon, Sitanshu Gupta, Sumti Jairath, Matheen Musaddiq
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Publication number: 20180284864Abstract: A method for dynamic clock and voltage scaling (DCVS) in a central processing unit (CPU) subsystem of a wireless communication device. The method may be implemented by a DCVS controller of the wireless communication device. The DCVS controller monitors data packets communicated by the CPU subsystem over a wireless local area network (WLAN) and determines one or more metrics of the data packets communicated by the CPU subsystem. The DCVS controller then dynamically configures an operating frequency of one or more hardware resources of the CPU subsystem based at least in part on the one or more metrics. The one or more metrics may include, for example, a packet rate, payload size, aggregation factor, packet size, or number of descriptors associated with the data packets.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Sandip HomChaudhuri, Amitabh Menon, Srikant Kuppa, Pradeep Kumar Yenganti, Subramania Sharma Thandaveswaran, Harpreet Singh Saluja, Pankaj Deshpande
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Patent number: 9465753Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.Type: GrantFiled: July 13, 2015Date of Patent: October 11, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph Raymond Michael Zbiciak, Amitabh Menon
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Patent number: 9239798Abstract: A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.Type: GrantFiled: September 15, 2011Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew D Pierson, Joseph R M Zbiciak, Kai Chirca, Amitabh Menon, Timothy D Anderson
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Publication number: 20150317259Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Inventors: Joseph Raymond Michael Zbiciak, Amitabh Menon
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Patent number: 9110845Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.Type: GrantFiled: August 1, 2011Date of Patent: August 18, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph R. M. Zbiciak, Amitabh Menon
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Patent number: 8806110Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.Type: GrantFiled: September 21, 2011Date of Patent: August 12, 2014Assignee: Texas Instruments IncorporatedInventors: Joseph R. M. Zbiciak, Amitabh Menon, Timothy D. Anderson
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Patent number: 8732370Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.Type: GrantFiled: August 18, 2011Date of Patent: May 20, 2014Assignee: Texas Instruments IncorporatedInventors: Kai Chirca, Timothy D Anderson, Amitabh Menon
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Patent number: 8732551Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.Type: GrantFiled: September 20, 2011Date of Patent: May 20, 2014Assignee: Texas Instruments IncoporatedInventors: Kai Chirca, Timothy D. Anderson, Amitabh Menon
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Patent number: 8683114Abstract: A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.Type: GrantFiled: September 21, 2011Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Joseph R. M. Zbiciak, Amitabh Menon
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Publication number: 20120239895Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.Type: ApplicationFiled: August 1, 2011Publication date: September 20, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph R. M. Zbiciak, Amitabh Menon
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Publication number: 20120191933Abstract: A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.Type: ApplicationFiled: September 21, 2011Publication date: July 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph R.M. Zbiciak, Amitabh Menon
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Publication number: 20120191899Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.Type: ApplicationFiled: September 21, 2011Publication date: July 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph R. M. Zbiciak, Amitabh Menon, Timothy D. Anderson
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Publication number: 20120072702Abstract: A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.Type: ApplicationFiled: September 15, 2011Publication date: March 22, 2012Inventors: Matthew D. Pierson, Joseph R.M. Zbiciak, Kai Chirca, Amitabh Menon, Timothy D. Anderson
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Publication number: 20120072796Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.Type: ApplicationFiled: September 20, 2011Publication date: March 22, 2012Inventors: Kai Chirca, Timothy D. Anderson, Amitabh Menon
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Publication number: 20120072631Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.Type: ApplicationFiled: August 18, 2011Publication date: March 22, 2012Inventors: Kai Chirca, Timothy D. Anderson, Amitabh Menon
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Patent number: 7725687Abstract: This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.Type: GrantFiled: June 27, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Amitabh Menon, David J. Hoyle
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Patent number: 7673120Abstract: A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.Type: GrantFiled: June 27, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: David J. Hoyle, Amitabh Menon
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Publication number: 20090006816Abstract: A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.Type: ApplicationFiled: June 27, 2007Publication date: January 1, 2009Inventors: David J. Hoyle, Amitabh Menon
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Publication number: 20080016320Abstract: This invention uses vector predicate registers to control conditional execution of instructions for vector elements within a data word. A particular vector predicate registers is addressed via a register index. The state of bits of the vector predicate register controls whether a corresponding sub-word operation is executed or inhibited.Type: ApplicationFiled: June 27, 2007Publication date: January 17, 2008Inventors: Amitabh Menon, David Hoyle