Abstract: A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization.

Abstract: A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Abstract: A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

Abstract: Techniques for generating variants of a circuit layout and evaluating quality of the variants are provided. In one aspect, a method for generating at least one variant layout for a cell design includes the following steps. At least a first basis layout and a second basis layout are obtained for the cell design, each having a plurality of shapes, each of the shapes being a polygon having a plurality of sides and vertices. One or more of the shapes in the first basis layout are linked with one or more of the shapes in the second basis layout that represent a common feature of the cell design resulting in a plurality of linked shapes. Starting with either the first basis layout or the second basis layout, a location of the vertices of each of the linked shapes are changed to produce the variant layout for the cell design.

Abstract: A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

Abstract: A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.

Abstract: A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization.

Abstract: A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows.

Abstract: A method and system for rapidly modeling and simulating intra-die variations in an integrated circuit are disclosed. In one embodiment, each logic gate in an integrated circuit has a characteristic to be simulated, where the characteristic of the gate is a function of one or more parameters having intra-die variations. For each parameter, a model of intra-die variation of the parameter is generated such that a number of random variables in the model is compressed to a reduced number (r) of random variables based on a spatial correlation of the intra-die variation of the parameter. Then, using a Quasi Monte Carlo (QMC) technique, the integrated circuit is simulated based on the model of the intra-die variation of each of the one or more parameters.

Abstract: Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

Abstract: The invention provides methods for enhancing circuit reliability under statistical process variation. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. To combat this, the invention discloses the method called “Statistical Blockade,” a Monte Carlo-type technique that allows the efficient filtering—blocking—of unwanted samples insufficiently rare in the tail distributions of interest, with speedups of 10-100×. Additionally, the core Statistical Blockade technique is further extended in a “recursive” or “bootstrap” formulation to create even greater efficiencies under a much wider variety of circuit performance metrics, in particular two-sided metrics such a Data Retention Voltage (DRV) which prior Monte Carlo techniques could not handle.

Abstract: A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.

Abstract: A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization.

Abstract: A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at various location in the drawn layout. This placement is done in such manner that contours of shapes in the drawn layout intersect a chord in at least two places. The length of the chord is defined as its portion delimited by the intersections, and a measurement of the chord is defined as obtaining its length. The drawn layout is subjected, with the exception of the chords, to a patterning simulation at a selected processing point. Following the simulation the chords are measured and the obtained lengths associated with the drawn layout and the processing point. The patterning simulation may be carried out at a variety processing points and the chord lengths following each simulation are associated with the respective processing point.

Abstract: Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

Abstract: A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values.

Abstract: A method and apparatus for determining overlay includes an array of electronic devices having structures formed in a plurality of layers and such that a device on a first end of the array includes an offset from a position of a device on a second end of the array. A measurement device is configured to measure electrical characteristics of the devices in the array to determine a transition position between the electrical characteristics. A comparison device is configured to determine an overlay between the layers based on a device associated with the transition position.

Abstract: A method and system for modeling uncertainties in integrated circuits, systems and fabrication processes may include defining interval values for each uncertain component or parameter in a circuit or system. The method may also include replacing scalar operations with interval operations in an algorithm and discontinuing interval operations in the algorithm in response to a predetermined condition. The method may also include generating a plurality of scalar samples from a plurality of intervals and determine a distribution of each uncertain component or parameter from the scalar samples of the intervals.