Patents by Inventor Amiya R. Ghatak-Roy

Amiya R. Ghatak-Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6579788
    Abstract: A method of forming conductive interconnections is disclosed herein. In one illustrative embodiment, the method comprises forming an opening in a layer of insulation material, forming a first plurality of silicon seed atoms in the opening, and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms in the opening above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms to further form tungsten material in the opening.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: June 17, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Clive Martin Jones, Tim Z. Hossain, Amiya R. Ghatak-Roy
  • Patent number: 6284636
    Abstract: A tungsten gate electrode and method of fabricating the same are provided. In one aspect, a method of fabricating a gate electrode stack on a substrate is provided that includes forming an insulating film on the substrate and forming a conductor film on the insulating film by initially depositing a film of amorphous silicon and amorphous tungsten, and thereafter depositing a film of polycrystalline tungsten on the film and annealing the substrate to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film. The tungsten silicide film and the polycrystalline tungsten film are patterned to define the gate electrode stack. The method enables the seamless fabrication of an adhesion layer and a tungsten gate in a single chamber and without resort to titanium.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: September 4, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Timothy Z. Hossain, Amiya R. Ghatak-Roy, Jason B. Zanotti
  • Patent number: 6274472
    Abstract: A tungsten gate electrode and method of fabricating the same are provided. In one aspect, a method of fabricating a circuit device in an opening in an insulating film on a substrate is provided. The method includes depositing a film of amorphous silicon and amorphous tungsten in the opening, and thereafter depositing a film of polycrystalline tungsten on the film and annealing the substrate to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film. The tungsten silicide film and the polycrystalline tungsten film may be planarized to the insulating film. The method enables the seamless fabrication of an adhesion layer and a tungsten conductor structure in a single chamber and without resort to titanium.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: August 14, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Timothy Z. Hossain, Amiya R. Ghatak-Roy, Allen Evans
  • Patent number: 6242785
    Abstract: A transistor and a method for making a transistor are described. A silicon gate conductor is patterned over a gate dielectric upon a silicon substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. Silicon nitride (“nitride”) spacers are formed adjacent to opposed sidewall surfaces of the gate conductor. Oxide caps are formed covering exposed outer surfaces of the nitride spacers. The oxide caps prevent dissociation of the nitride spacers during a subsequent pre-amorphization implant. A preclean is subsequently used to remove oxides from the surfaces of the gate conductor and semiconductor substrate. The preclean may also remove the oxide caps, but does not attack the nitride spacers. A salicide process is used to form low-resistance gate, source, and drain silicides.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: June 5, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tim Z. Hossain, Amiya R. Ghatak-Roy, Clive Jones
  • Patent number: 6156650
    Abstract: A method of making a semiconductor device to reduce or prevent defects caused by the ejection of deposited material. The method includes a first layer of material deposited over a substrate in the presence of a gaseous ambient. A portion of the gaseous ambient is trapped by the first layer. This entrapped portion could cause defects during subsequent elevated temperature processing as the gas attempts to escape from the first layer. To prevent or reduce this problem, after depositing the first layer and before depositing a second layer over the first layer, the first layer is heated to remove at least a portion of the gaseous ambient trapped in the layer. For best results, the first layer is heated to a temperature at least as high as the highest temperature of later processing steps and at a pressure of no more than 1 torr. This method is particularly useful for layers formed by physical vapor deposition.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: December 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tim Z. Hossain, William S. Brennan, Berta Valdez, Renee S. Prusik, Amiya R. Ghatak-Roy