Abstract: A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for executing a memory specific test sequence to detect faults in memory (20). The microcode processor (1130) further communicates with a repair state machine (1150) to execute memory specific repair procedures responsive to memory faults being detected.

Abstract: A method, system and apparatus of a secure debug interface and memory of a media security circuit and method are disclosed. In one embodiment, a host processor, an external hardware circuit to encrypt an incoming data bit communicated to a debug interface using a debug master key stored at a pointer location of a memory (e.g., the memory may be any one of a flash memory and/or an Electrically Erasable Programmable Read-Only Memory (EEPROM)) and to decrypt an outgoing data bit from the debug interface using the debug master key, and a media security circuit having the debug interface to provide the pointer location of the memory having the debug master key to the external hardware circuit.

Abstract: A method includes encrypting, in a security engine associated with a memory/storage controller of a memory/storage device in a data processing device, a pre-encrypted/unencrypted data stream associated with a multimedia content in accordance with a data write request to transfer the pre-encrypted/unencrypted data stream to the memory/storage device using a security key configured to uniquely identify the data processing device during each data write session and a security flag configured to uniquely identify each data write session during a secure mode of operation. The method also includes transmitting the security engine encrypted data stream to the memory/storage device in accordance with the data write request, and decrypting the security engine encrypted data stream using the security key and the security flag in accordance with a data read request to read the security engine encrypted data stream stored in the memory/storage device.

Abstract: The method, system, and apparatus of key exchange through a scramble methodology and system is disclosed. In one embodiment, the method includes generating a security key associated with a protected media content, disassembling the security key (e.g., may be an unencrypted key) into a set of key bits, generating non-key bits (e.g., may be arbitrarily and/or randomly created binary numbers), placing the non-key bits disbursed between at least some of the set of key bits based on an algorithm of a control register module of a scatter module, algorithmically specifying a number of the set of key bits and the non-key bits in a packet, and communicating the packet and other packets each having the non-key bits disbursed between at least some the set of key bits of each of the packet and the other packets to a gather module.

Abstract: A method, system and apparatus of a secure debug interface and memory of a media security circuit and method are disclosed. In one embodiment, a host processor, an external hardware circuit to encrypt an incoming data bit communicated to a debug interface using a debug master key stored at a pointer location of a memory (e.g., the memory may be any one of a flash memory and/or an Electrically Erasable Programmable Read-Only Memory (EEPROM)) and to decrypt an outgoing data bit from the debug interface using the debug master key, and a media security circuit having the debug interface to provide the pointer location of the memory having the debug master key to the external hardware circuit.

Abstract: A method, system and apparatus of an author website in a commerce environment are disclosed. In one embodiment, a system includes a host processor; a first security circuit to re-encrypt a work of authorship protected by an encryption standard using a proprietary key after an authorization module uses an algorithm of the encryption standard to verify that the system has permission to playback the work of authorship; a system memory to store a proprietary encrypted content generated through the re-encryption process of the first security circuit; and a second security circuit of a display module to independently generate the proprietary key using an index pointer provided from the first security circuit to the second security circuit through the host processor and to decrypt the proprietary encrypted content of the system memory using the independently generated proprietary key.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or “bus wrapper”. “Peripheral” virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a “plug and play’ capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.

Abstract: A computer system includes three processors capable to operate concurrently—a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory.

Abstract: JTAG test logic and a memory controller place an SDRAM in a self refresh mode prior to beginning JTAG testing. The memory controller can complete a current memory access and otherwise prepare for the JTAG test. During the JTAG test, self refresh mode operation of the SDRAM retains data without the need for a clock signal or refresh signals which are suspended for the JTAG test. Accordingly, after the JTAG test, circuit operation can continue without reinitializing data in the SDRAM.