Patents by Inventor Amna Shawwa

Amna Shawwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory apparatus and signal delay circuit for generating delayed column select signal
    Patent number: 8861291
    Abstract: The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 14, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Amna Shawwa, Phat Truong
  • MEMORY APPARATUS AND SIGNAL DELAY CIRCUIT FOR GENERATING DELAYED COLUMN SELECT SIGNAL
    Publication number: 20140160873
    Abstract: The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Inventors: Amna Shawwa, Phat Truong