Abstract: A networking device/storage device direct write system includes a chassis that houses a Solid State Drive (SSD) storage device coupled to a Smart Network Interface Controller (SmartNIC) networking device. The SmartNIC networking device receives data via a network, stores the data in a SmartNIC buffer memory subsystem that is included in the SmartNIC networking device, and then perform a Direct Memory Access (DMA) operation to transfer the data stored in the SmartNIC buffer memory subsystem to an addressable memory subsystem that is included in the SSD storage device. If the addressable memory subsystem in the SSD storage device is a volatile memory subsystem, the SmartNIC networking device then transmits a persistent storage instruction to the SSD storage device that causes the SSD storage device to transfer the data stored in the addressable memory subsystem to a persistent memory subsystem in the SSD storage device.

Abstract: Techniques described herein relate to a method for performing computational offloads for composed information handling systems. The method includes obtaining, by a system control processor associated with a composed information handling system, a computational offload request associated with a dataset from an application executing on an at least one compute resource set; in response to obtaining the computational offload request: identifying a dataset location associated with the dataset in the composed information handling system; identifying resources of the composed information handling system capable of performing the computational offload request; selecting a resource of the resources to perform the computational offload; and initiating performance of the computational offload request on the selected resource.

Abstract: Systems and methods provide alternative store-and-forward mechanisms to utilize a Non-Volatile Memory Express (NVMe™) drive's Controller Memory Buffer (CMB) instead of using a fabric bridge's memory resources to increase overall throughput. In various embodiment this successfully avoids performance scaling limitations of a centralized store-and-forward memory location for data input/output, within a large disk-array, that may otherwise oversubscribe the available memory space.

Abstract: A networking device/storage device direct write system includes a chassis that houses a Solid State Drive (SSD) storage device coupled to a Smart Network Interface Controller (SmartNIC) networking device. The SmartNIC networking device receives data via a network, stores the data in a SmartNIC buffer memory subsystem that is included in the SmartNIC networking device, and then perform a Direct Memory Access (DMA) operation to transfer the data stored in the SmartNIC buffer memory subsystem to an addressable memory subsystem that is included in the SSD storage device. If the addressable memory subsystem in the SSD storage device is a volatile memory subsystem, the SmartNIC networking device then transmits a persistent storage instruction to the SSD storage device that causes the SSD storage device to transfer the data stored in the addressable memory subsystem to a persistent memory subsystem in the SSD storage device.

Abstract: A method, computer program product, and computing system for receiving a plurality of data streams on an SSD cache memory system associated with a backend storage system and writing a first of the plurality of data streams to a first portion of the SSD cache memory system.

Abstract: A storage system in one embodiment comprises a host processor, and a solid-state storage device coupled to the host processor and comprising a non-volatile memory and a storage controller. The host processor is configured to initiate an error scanning operation on a designated portion of the non-volatile memory by directing at least one read command to the storage controller. The read command is configured to indicate to the storage controller that data read from the non-volatile memory responsive to the read command is not to be returned to the host processor. For example, the read command may illustratively comprise a Scatter Gather List (SGL) bit bucket descriptor indicating that the data read from the non-volatile memory responsive to the read command is to be discarded rather than returned to the host processor. The storage controller records any detected errors in a media error log and notifies the host processor of such errors.

Abstract: A first endpoint comprises a fabric attach point for attachment to a memory fabric, a first media controller, and a first non-volatile memory media. The memory fabric comprises a reliability zone comprising the first endpoint and at least a second endpoint. The first media controller is configured to receive, from at least one processor coupled to the first endpoint via the at least one fabric attach point, a memory fabric store command to store an object in the reliability zone. The first media controller is further configured to store the object in the first non-volatile memory media, to receive from the second endpoint a message indicating that the same object has been stored by the second endpoint, and to send to the at least one processor a single acknowledgement indicating that the at least one object has been stored in both the first and second endpoints of the reliability zone.

Abstract: A method, computer program product, and computing system for receiving a plurality of data streams on an SSD cache memory system associated with a backend storage system and writing a first of the plurality of data streams to a first portion of the SSD cache memory system.

Abstract: A method, computer program product, and computing system for receiving a plurality of data streams on an SSD cache memory system associated with a backend storage system and writing a first of the plurality of data streams to a first portion of the SSD cache memory system.

Abstract: A storage system in one embodiment comprises a host processor, a volatile memory associated with the host processor, and a solid-state storage device comprising a non-volatile memory. The host processor is configured to detect a particular power condition, such as a power failure condition, and responsive to the detected power condition to direct the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device. In conjunction with directing the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device, the host processor further directs the solid-state storage device to enter an enhanced write bandwidth operating mode in which the solid-state storage device temporarily at least partially suspends at least one specified background process that would otherwise tend to restrict an achievable write bandwidth of the solid-state storage device.

Abstract: A method includes obtaining instructions at a mobile device comprising directions from a current location of the mobile device to a target location in a facility over a path identified by two or more waypoint devices distributed in the facility, receiving signaling over at least one wireless network from a selected one of the waypoint devices in the path, utilizing a radio frequency signal strength of the received signaling to estimate proximity between the mobile device and the selected waypoint device, presenting an indication of proximity to the first waypoint device via the mobile device based at least in part on the estimated proximity, determining whether the estimated proximity between the mobile device and the selected waypoint device is below a proximity threshold, and selecting another one of the waypoint devices in the path responsive to determining that the estimated proximity is below the proximity threshold.

Abstract: A system, computer program product, and computer-executable method of managing a solid state drive (SSD) in a data storage system, the system, computer program product, and computer-executable method including initializing the SSD to enable the SSD to request memory for bad block replacement, querying the SSD to determine a size of memory on the SSD reserved for dynamic over provisioning, and allocating a portion of the size of memory for bad block replacement.

Abstract: A data processing system stores encrypted data. Object identifiers are assigned to storage objects, and data encryption keys are assigned to the storage objects. When performing an operation upon a storage object, data encryption key failure may occur due to a corrupt or incorrect key. In this case, a copy of the data encryption key is fetched from a key server. It is possible for the association of the object identifiers with the data encryption keys to become lost or confused, so that the key server may fail to provide the correct key for a specified object identifier. Therefore, an absolute key identifier that is unique across the key server namespace also is stored in association with the object identifier in the storage system and in the key store of the key server, and the absolute key identifier is used as a failsafe for recovery of encrypted data.

Abstract: A method, computer program product, and computing system for receiving an unsecure data portion for storage within a storage system. The unsecure data portion is stored within a temporary storage device. The unsecure data portion is processed to produce a secure data portion via a processor included within a first controller card included within the storage system. The secure data portion is stored on a persistent storage device via a second controller card.

Abstract: A method, computer program product, and computing system for storing an unsecure data portion within a temporary storage device. An indication of a power failure event within the storage system is received. The unsecure data portion is processed to produce a secure data portion via a processor included within a first controller card included within the storage system. The secure data portion is stored on a persistent storage device via a second controller card.

Abstract: A method, computer program product, and computing system for storing an unsecure data portion within a temporary storage device. An indication of a power failure event within the storage system is received. The unsecure data portion is processed to produce a secure data portion via a processor included within a first controller card included within the storage system. The secure data portion is stored on a persistent storage device via a second controller card.

Abstract: A method, computer program product, and data storage system for associating an encryption key with each of a plurality of storage objects within a data storage system, thus defining a plurality of encryption keys. Each of the plurality of encryption keys is appended to include a key identifier tag, thus defining a plurality of tagged encryption keys. The key identifier tag included within each tagged encryption key identifies the storage object with which the tagged encryption key is associated.

Abstract: A data processing system stores encrypted data. Object identifiers are assigned to storage objects, and data encryption keys are assigned to the storage objects. When performing an operation upon a storage object, data encryption key failure may occur due to a corrupt or incorrect key. In this case, a copy of the data encryption key is fetched from a key server. It is possible for the association of the object identifiers with the data encryption keys to become lost or confused, so that the key server may fail to provide the correct key for a specified object identifier. Therefore, an absolute key identifier that is unique across the key server namespace also is stored in association with the object identifier in the storage system and in the key store of the key server, and the absolute key identifier is used as a failsafe for recovery of encrypted data.

Abstract: An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the interrupt level. In other words, a CPU is able to block one or more individual interrupt requests from I/O devices from being sent to that CPU. Second, each CPU is able to block interrupts from one or more entire MSI interrupt registers from being sent to that CPU. The interrupt controller is fully programmable by the CPUs in software and thus is very flexible, as the priority of interrupts can be controlled by the CPUs according to the requirements of the CPUs based on the various operational demands of the CPUs. Any of 512 possible interrupt requests are capable of being routed to any particular one CPU, any combination of the CPUs or to all of the CPUs.