Patents by Inventor Amod Phadke

Amod Phadke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mitigation of duty-cycle distortion
    Patent number: 11881862
    Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Udayakiran Kumar Yallamaraju, Xia Li, Pankaj Deshmukh, Vajram Ghantasala, Bin Yang, Vishal Mishra, Bharatheesha Sudarshan Jagirdar, Arun Sundaresan Iyer, Amod Phadke, Vanamali Bhat
  • MITIGATION OF DUTY-CYCLE DISTORTION
    Publication number: 20230058318
    Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 23, 2023
    Inventors: Udayakiran Kumar YALLAMARAJU, Xia LI, Pankaj DESHMUKH, Vajram GHANTASALA, Bin YANG, Vishal MISHRA, Bharatheesha Sudarshan JAGIRDAR, Arun Sundaresan IYER, Amod PHADKE, Vanamali BHAT
  • Clock monitoring unit with serial clock routing pipeline
    Patent number: 11327525
    Abstract: An apparatus including a serial clock routing pipeline including a first set of clock inputs and a clock output; a first set of clock generators including a first set of clock outputs coupled to the first set of clock inputs of the serial clock routing pipeline, respectively; and a first clock monitoring unit including a first clock input coupled to the clock output of the serial clock routing pipeline, and a first status output to provide information concerning one or more of the first set of clock generators. The apparatus may further include a set of phase locked loops (PLLs) coupled to the set of clock generators, respectively; the set of PLLs also coupled to the clock monitoring unit.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 10, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Federico Salluzzo, Sina Dena, Amod Phadke, Vanamali Bhat