Abstract: An apparatus to facilitate summarizing stimulus space via clustering and stochastic processes is disclosed. The apparatus includes processing circuitry to: receive an original set of stimuli input data, the stimuli input data comprises variables for input to an electronic circuit simulator to check an integrity of integrated circuit designs and to predict integrated circuit behavior; apply a clustering algorithm to the original set to determine k subsets of the original set; define, for each subset of the k subsets, a random variable per subset in accordance with a distribution corresponding to the subset; compute inter-cluster transition probabilities between the k subsets; sample, in accordance with the inter-cluster transition probabilities, a reduced set of the stimuli input data from the k subsets of the original set; and utilize the reduced set as a smaller representative set of the stimuli input data for input to the electronic circuit simulator.

Abstract: An apparatus to facilitate distinct paths counterexamples and stimuli generation is disclosed. The apparatus includes processing circuitry to: generate a graph representation structure from a data flow of a hardware design; for each leaf node of the graph representation structure, generate a cover property that is to provide a set of space constraints of the graph representation structure and to query whether a verification property is satisfied by the hardware design having the set of space constraints applied, wherein the set of space constraints define a path through the graph representation structure from a root node to the leaf node; execute, as a single run of a verification tool, a set of cover properties comprising the cover property for each of the leaf nodes; and report results of execution of the set of cover properties as a set of counterexamples for the hardware design.

Abstract: A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of events in testing a semiconductor design is disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer for processing. A determination is made as to which test sequences trigger events not already triggered by previously-considered test sequences. An autograde data structure is generated which further reduces the number of test sequences. A preferred embodiment of the present invention may be used to reduce the number of test sequences required, but may also be used to provide test engineers a basis for devising manually-created test sequences to test related events.

Abstract: A method, computer program product, and data processing system for determining test sequences' coverage of events in testing a semiconductor design are disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer in the form of an ordered dictionary of events and bitmap and/or countmap data structures. A “bitmap” data structure encodes Boolean information regarding whether or not a given event was covered by a particular test sequence. A “countmap” data structure includes frequency information indicating how many times a given event was triggered by a particular test sequence. The backend computer combines results from each test sequence in a cumulative fashion to measure the overall coverage of the set of test sequences.