Patents by Inventor Amol Joshi
Amol Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230281762Abstract: Various examples are provided related to fingerphoto deblurring. In one example, a method includes generating, using a guided-attention (GA) mechanism, an intermediate feature map of a blurred image of a fingerprint and generating a deblurred image of the fingerprint based at least in part upon the intermediate feature map. The GA mechanism can generate the intermediate feature map by generating an attended feature map from an input feature map based upon a predicted attention map and adding the input feature map to the attended feature map. A system can include processing circuitry and a fingerphoto deblurring application that, when executed by the processing circuitry, causes the processing circuitry to generate the intermediate feature map and generate the deblurred image.Type: ApplicationFiled: February 22, 2023Publication date: September 7, 2023Inventors: Nasser M. Nasrabadi, Jeremy M. Dawson, Amol Joshi, Ali Dabouei
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Patent number: 11035127Abstract: A building system including a first water resistant layer secured to a building substrate, first and second building articles secured to the first water resistant layer and the building substrate such that sides of the building articles are positioned adjacent one another along an abutment line, and a second water resistant layer secured to portions of the first and second building articles along the abutment line to prevent liquid from traveling past the sides of the building articles to the first water resistant layer and the building substrate. In some embodiments, the building articles are fiber cement building articles. In some embodiments, the building articles include a plurality of integrally formed drainage channels and a plurality of spacer sections disposed between the drainage channels, each of the plurality of drainage channels defining an air gap comprising a liquid flow path.Type: GrantFiled: November 6, 2019Date of Patent: June 15, 2021Assignee: James Hardie Technology LimitedInventors: Amol Joshi, Brian McQuerrey, Hui Li, Noel A. Dones
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Patent number: 10900221Abstract: The present application is generally directed to multifunctional flashing devices suitable for installation of lap siding. Flashing devices include a flashing section, a removable supporting section, and one or more alignment features configured to facilitate positioning of the flashing devices adjacent to an installed course of lap siding. The flashing devices may be fastened to a building substrate adjacent to an installed course of lap siding, at locations corresponding to butt joints of an additional course of lap siding. The supporting sections of the flashing devices are configured to retain and support additional cladding elements in position for installation. When the additional cladding elements have been fastened to the building substrate, the supporting section may be removed from the flashing section.Type: GrantFiled: December 17, 2019Date of Patent: January 26, 2021Assignee: James Hardie Technology LimitedInventors: Michael McEndree, Richard Klein, Hui Li, Amol Joshi, Thayne Dye
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Publication number: 20200199865Abstract: The present application is generally directed to multifunctional flashing devices suitable for installation of lap siding. Flashing devices include a flashing section, a removable supporting section, and one or more alignment features configured to facilitate positioning of the flashing devices adjacent to an installed course of lap siding. The flashing devices may be fastened to a building substrate adjacent to an installed course of lap siding, at locations corresponding to butt joints of an additional course of lap siding. The supporting sections of the flashing devices are configured to retain and support additional cladding elements in position for installation. When the additional cladding elements have been fastened to the building substrate, the supporting section may be removed from the flashing section.Type: ApplicationFiled: December 17, 2019Publication date: June 25, 2020Inventors: Michael McEndree, Richard Klein, Hui Li, Amol Joshi, Thayne Dye
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Patent number: 10652103Abstract: A method includes receiving, at a fabric monitoring system, information identifying occurrences of events in an enterprise system having multiple computing or networking systems. The events occur on or involve computing or networking devices in the computing or networking systems, and the events are identified using rules accessible by the fabric monitoring system. The method also includes processing, using the fabric monitoring system, the information in real-time to identify the occurrences of the events and to assign the events to multiple situations. The events are assigned to the situations using one or more processing models accessible by the fabric monitoring system. The method further includes outputting information identifying the situations.Type: GrantFiled: April 20, 2016Date of Patent: May 12, 2020Assignee: Goldman Sachs & Co. LLCInventors: Robert Anderson, Ilia Berman, Keith Billis, Amol Joshi
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Publication number: 20200071935Abstract: A building system including a first water resistant layer secured to a building substrate, first and second building articles secured to the first water resistant layer and the building substrate such that sides of the building articles are positioned adjacent one another along an abutment line, and a second water resistant layer secured to portions of the first and second building articles along the abutment line to prevent liquid from traveling past the sides of the building articles to the first water resistant layer and the building substrate. In some embodiments, the building articles are fiber cement building articles. In some embodiments, the building articles include a plurality of integrally formed drainage channels and a plurality of spacer sections disposed between the drainage channels, each of the plurality of drainage channels defining an air gap comprising a liquid flow path.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Amol Joshi, Brian McQuerrey, Hui Li, Noel A. Dones
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Patent number: 10519673Abstract: A wall cladding panel comprising a substantially planar front face, a rear face comprising a plurality of drainage channels and a plurality of spacer sections disposed between the drainage channels, and an edge member disposed contiguously between the front face and the rear face. The wall cladding panel is locally thinner at the drainage channels than at the spacer sections. Each drainage channel is configured to form a liquid flow path and/or an air gap when a substantially planar building surface is placed adjacent to the rear face. A plurality of wall cladding panels with drainage channels may be arranged in series to cover at least a portion of a building.Type: GrantFiled: December 22, 2016Date of Patent: December 31, 2019Assignee: James Hardie Technology LimitedInventors: Amol Joshi, Brian McQuerrey, Hui Li
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Publication number: 20180328044Abstract: A wall cladding panel comprising a substantially planar front face, a rear face comprising a plurality of drainage channels and a plurality of spacer sections disposed between the drainage channels, and an edge member disposed contiguously between the front face and the rear face. The wall cladding panel is locally thinner at the drainage channels than at the spacer sections. Each drainage channel is configured to form a liquid flow path and/or an air gap when a substantially planar building surface is placed adjacent to the rear face. A plurality of wall cladding panels with drainage channels may be arranged in series to cover at least a portion of a building.Type: ApplicationFiled: December 22, 2016Publication date: November 15, 2018Inventors: Amol Joshi, Brian McQuerrey, Hui Li
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Publication number: 20160315822Abstract: A method includes receiving, at a fabric monitoring system, information identifying occurrences of events in an enterprise system having multiple computing or networking systems. The events occur on or involve computing or networking devices in the computing or networking systems, and the events are identified using rules accessible by the fabric monitoring system. The method also includes processing, using the fabric monitoring system, the information in real-time to identify the occurrences of the events and to assign the events to multiple situations. The events are assigned to the situations using one or more processing models accessible by the fabric monitoring system. The method further includes outputting information identifying the situations.Type: ApplicationFiled: April 20, 2016Publication date: October 27, 2016Inventors: Robert Anderson, Ilia Berman, Keith Billis, Amol Joshi
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Publication number: 20160181380Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
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Patent number: 9362283Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: GrantFiled: July 7, 2015Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Patent number: 9323875Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.Type: GrantFiled: February 28, 2012Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Peter A. Habitz, Amol A. Joshi, Amith Singhee, James E. Sundquist, Wangyang Zhang
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Patent number: 9312137Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).Type: GrantFiled: October 31, 2013Date of Patent: April 12, 2016Assignee: Intermolecular, Inc.Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
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Publication number: 20160093711Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.Type: ApplicationFiled: June 25, 2014Publication date: March 31, 2016Inventors: Zhendong Hong, Paul Besser, Kisik Choi, Amol Joshi, Olov Karlsson, Susie Tzeng
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Patent number: 9276007Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: January 29, 2014Date of Patent: March 1, 2016Assignee: Cypress Semiconductor CorporationInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Publication number: 20150380309Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.Type: ApplicationFiled: June 26, 2014Publication date: December 31, 2015Inventors: Salil Mujumdar, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, Bin Yang
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Patent number: 9224644Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.Type: GrantFiled: December 26, 2012Date of Patent: December 29, 2015Assignee: Intermolecular, Inc.Inventors: Sandip Niyogi, Amol Joshi, Chi-I Lang, Salil Mujumdar
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Publication number: 20150311206Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Patent number: D906552Type: GrantFiled: December 21, 2018Date of Patent: December 29, 2020Assignee: James Hardie Technology LimitedInventors: Michael McEndree, Richard Klein, Amol Joshi, Hui Li, Thayne Dye
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Patent number: D962491Type: GrantFiled: March 25, 2021Date of Patent: August 30, 2022Assignee: James Hardie Technology LimitedInventors: Amol Joshi, Thomas Patrick Mueller