Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.

Abstract: According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.

Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. A thermally grown oxide liner is situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process.

Abstract: According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.

Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of the base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further includes a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also includes a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further includes a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may include, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.

Abstract: According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.