Abstract: A method is provided of integrating the formation of nanotube devices on the same substrate or wafer as CMOS devices in a standard CMOS process. During a CMOS formation process, a region of the substrate containing CMOS devices is protected from certain nanotube fabrication processes while fabricating nanotube devices on the substrate. After fabrication of the nanotube devices, the region of the substrate containing the fabricated nanotube devices is then protected from certain CMOS fabrication processes while fabricating CMOS devices on a different region of the same substrate. Through this formation method, a nanotube device based RF/analog system-on-chip (SoC) application can be formed having the superior RF/analog properties of nanotube electronic circuitry and the superior digital properties of silicon CMOS circuitry on the same wafer or substrate.

Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.

Abstract: A method is provided for determining the anisotropy of alignment of a random array of 1-D conductive elements (e.g., carbon nanotube or silicon nanowire) formed on a substrate. A pattern of a plurality of electrodes are arranged on the substrate containing the 1-D conductive elements and a plurality of electrical property measurements are performed in a plurality of different directions between the plurality of electrodes. The plurality of measurements are combined together to generate a total measurement sum of electrical property measurements between the various electrodes. The measured electrical property is determined between a selected pair of the plurality of electrodes along a selected direction extending between the selected pair of electrodes. The anisotropy of alignment of the 1-D conductive elements on the substrate along the selected direction is determined based on a ratio of the measured electrical property between the selected pair of electrodes versus the total measurement sum.

Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Abstract: An integrated, multilayer nanotube and complementary metal oxide semiconductor (CMOS) device is provided along with a method of forming the same. The device includes at least one CMOS device formed on at least one layer of the device, a first metal wiring layer that is electrically connected to the least one CMOS device, and at least one nanotube device formed over the first metal wiring layer in parasitic isolation from the at least one CMOS device. In one or more embodiments, the at least one CMOS device and the at least one nanotube device are located on different layers of a same semiconductor wafer chip to allow the wafer to be is used for system-on-chip (SoC) applications having RF/analog circuitry based on the least one nanotube device and digital circuitry based on the at least one CMOS device.

Abstract: A method is provided for determining the anisotropy of alignment of a random array of 1-D conductive elements (e.g., carbon nanotube or silicon nanowire) formed on a substrate. A pattern of a plurality of electrodes are arranged on the substrate containing the 1-D conductive elements and a plurality of electrical property measurements are performed in a plurality of different directions between the plurality of electrodes. The plurality of measurements are combined together to generate a total measurement sum of electrical property measurements between the various electrodes. The measured electrical property is determined between a selected pair of the plurality of electrodes along a selected direction extending between the selected pair of electrodes. The anisotropy of alignment of the 1-D conductive elements on the substrate along the selected direction is determined based on a ratio of the measured electrical property between the selected pair of electrodes versus the total measurement sum.

Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.

Abstract: A method is provided of integrating the formation of nanotube devices on the same substrate or wafer as CMOS devices in a standard CMOS process. During a CMOS formation process, a region of the substrate containing CMOS devices is protected from certain nanotube fabrication processes while fabricating nanotube devices on the substrate. After fabrication of the nanotube devices, the region of the substrate containing the fabricated nanotube devices is then protected from certain CMOS fabrication processes while fabricating CMOS devices on a different region of the same substrate. Through this formation method, a nanotube device based RF/analog system-on-chip (SoC) application can be formed having the superior RF/analog properties of nanotube electronic circuitry and the superior digital properties of silicon CMOS circuitry on the same wafer or substrate.

Abstract: A method is provided for forming metal contacts to nanotube devices in a standard CMOS process flow. In accordance with one feature, a method for forming source/drain contacts to nanotube devices acting as FETs is provided while minimizing metal contamination to the complementary metal oxide semiconductor (CMOS) circuitry in a standard CMOS process flow. The method includes forming nanotube devices on a semiconductor substrate during a front end process of a CMOS process flow, while forming metallic contacts for the nanotube devices during a back end process of the CMOS process flow. This enables the formation of nanotube devices to be integrated within a standard CMOS process flow, thereby opening avenues to commercializing new generation of RFCMOS technology where superior RF/analog circuitry based on nanotube devices can be combined with digital circuitry based on standard silicon CMOS.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.

Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a conformal layer situated over the sacrificial post. The conformal layer may comprise silicon oxide, for example. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second link spacers and a second thickness in a second region outside of the first and second link spacers, where the second thickness is generally greater than the first thickness. Another embodiment is a method that achieves the above-described bipolar transistor.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.