Abstract: A modulator and demodulator pair may switch configurations without introducing errors as a result of the switch. Different configurations may, for example, correspond to different symbol rates and/or different amounts of controlled inter-symbol interference (ISI) introduced to the transmitted signal. For example, a first configuration may use be a near-zero ISI configuration (e.g., using Nyquist signaling) and a second configuration may introduce a significant (e.g., amount that would result in errors above a desired threshold if demodulation relied on symbol-by-symbol slicing) but controlled amount of ISI (e.g., using partial response or faster-than-Nyquist-rate signaling). Switching between modulator/demodulator configurations may be needed to maintain a stable link in the case of dynamic channels. At any given time, a modulator and demodulator pair may, for example, switch to a configuration that provides maximal throughput for the current channel conditions.

Abstract: A modulator and demodulator pair may switch configurations without introducing errors as a result of the switch. Different configurations may, for example, correspond to different symbol rates and/or different amounts of controlled inter-symbol interference (ISI) introduced to the transmitted signal. For example, a first configuration may use be a near-zero ISI configuration (e.g., using Nyquist signaling) and a second configuration may introduce a significant (e.g., amount that would result in errors above a desired threshold if demodulation relied on symbol-by-symbol slicing) but controlled amount of ISI (e.g., using partial response or faster-than-Nyquist-rate signaling). Switching between modulator/demodulator configurations may be needed to maintain a stable link in the case of dynamic channels. At any given time, a modulator and demodulator pair may, for example, switch to a configuration that provides maximal throughput for the current channel conditions.

Abstract: A modulator and demodulator pair may switch configurations without introducing errors as a result of the switch. Different configurations may, for example, correspond to different symbol rates and/or different amounts of controlled inter-symbol interference (ISI) introduced to the transmitted signal. For example, a first configuration may use be a near-zero ISI configuration (e.g., using Nyquist signaling) and a second configuration may introduce a significant (e.g., amount that would result in errors above a desired threshold if demodulation relied on symbol-by-symbol slicing) but controlled amount of ISI (e.g., using partial response or faster-than-Nyquist-rate signaling). Switching between modulator/demodulator configurations may be needed to maintain a stable link in the case of dynamic channels. At any given time, a modulator and demodulator pair may, for example, switch to a configuration that provides maximal throughput for the current channel conditions.

Abstract: A receiver comprises a plurality of sequence estimation circuits. The receiver receives a signal that comprises a plurality of frames. For each one of the frames, the receiver samples the received signal resulting in a first plurality of samples corresponding to a preamble of the one of the frames and a second plurality of samples corresponding to a plurality of symbols of the one of the frames. A value of each sample of the second plurality of samples depends on several of the symbols of the one of the frames. The receiver splits the signal at preambles of the frames and demultiplexes the frames to generate a plurality of signals. The receiver may process the signals in parallel. The processing may comprise resetting of a state of each of the plurality of sequence estimation circuits upon detection of each preamble in a respective one of the plurality of signals.

Abstract: A method and apparatus for waking up a computer system using a peripheral device connected to a standard parallel port of the computer system. Functionality is added to the parallel port Select line normally used to indicate that the peripheral device connected to the parallel port is on line when the select signal is high. A signal transition on the Select line from low to high is detected and used to wake up the computer system. This toggling of the Selected line is detected and used to activate the computer system power supply into a normal operating state from a power save state.

Abstract: Apparatus and method for testing the connection (i.e. solder joint) between an input/output (I/O) pin of an integrated circuit and a conductive trace of a printed circuit board (PCB). The internal circuitry of the integrated circuit is isolated from each I/O pin, and a first voltage source is coupled to each I/O pin via a respective pull-up load resistor. A tester circuit is coupled to each conductive trace of the PCB and compares the voltage V.sub.T thereon with a high threshold level (HTVL) and a low threshold level (LTVL) to test for a proper connection. Voltage V.sub.T is derived for an I/O pin under test when a resistive element, which is part of the tester circuit, is operatively coupled between the corresponding conductive trace and a second voltage source. If V.sub.T is below the LTVL or above the HTVL, the I/O pin is improperly coupled to the conductive trace. If V.sub.T is between the LTVL and HTVL, then the voltage on each of the other traces is compared to the HTVL.

Abstract: An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: A method for monitoring the sequence of instructions executed by a central processing unit. When a branch instruction is executed, the central processing unit generates a representative interface signal. When a jump instruction is executed or an exception occurs, the central processing unit displays representative information on the external memory interface.

Abstract: The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency.

Abstract: An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks.