Patents by Inventor Amos Noy

Amos Noy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8296697
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 23, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy
  • Patent number: 7870523
    Abstract: The present invention provides a system and method for resolving a test generation problem involving constraint resolution problems where a verification environment includes constraints that are suitable for resolution using one type of solver for a first domain and other constraints that are suitable for resolution using a different solver in a second domain. The invention further comprises variables and, in instances where at least one variable is in each of the first and second domains, using these solvers to restrict the set of permissible values of variables to be consistent in multiple domains, preferably in all relevant domains. A constraint resolution problem is divided into clusters of constraints connected within a domain, and connected clusters of clusters that are connected through shared variables that are subject to constraints in more than one cluster.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 11, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shlomi Uziel, Amos Noy, Vitaly Lagoon, Yael Kinderman, Amit Gal
  • Publication number: 20080235640
    Abstract: Method and apparatus for performing static analysis optimization in a design verification system is described. In one example, a description of a verification environment having constrained objects is obtained. The constrained objects are analyzed incrementally to create a data structure of nodes. Each node includes a description of variables transitively connected by constraints. At least one of the nodes reuses a description from at least one other node. The data structure is then used during logic design verification.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Amit Gal, Shlomi Uziel, Amos Noy
  • Patent number: 7281185
    Abstract: A method and system for managing test generation and examination of test coverage so as to most efficiently obtain maximum coverage during test generation. Therefore, in addition to achieving coverage maximization, the present invention also preferably manages test generation in order to increase the efficiency of testing to obtain such coverage maximization. The present invention also preferably provides tactics and/or strategies for generation as part of such management. Thus, coverage providing by test generation and execution is not only measured, but is also preferably obtained in a more efficient manner by enabling the coverage maximization functions to provide feedback and management to the test generation process.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: October 9, 2007
    Assignee: Cadence Design (Israel) II Ltd.
    Inventors: Uri Maoz, Amos Noy
  • Patent number: 7114111
    Abstract: A method and an apparatus for determining functional coverage of a design for a device under test (DUT), the design being encapsulated in a DUT circuit design specification, in a test environment during a design test verification process. The method and apparatus utilize a coverage metric constructed from a plurality of coverage items. A first step involves obtaining a coverage group from the DUT design, for examining during the design test verification process. The coverage group includes at least one functional coverage item. Then, a set of input values is provided to the design test verification process. Next, design test verification process is performed with the set of input test values to obtain a value for each coverage item. Next step involves examining obtained coverage by comparing the value obtained from each coverage item with a coverage goal. Finally, the set of input test value is automatically altered in accordance with the examination of the obtained coverage.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: September 26, 2006
    Assignee: Cadence Design (Isreal) II Ltd.
    Inventor: Amos Noy
  • Publication number: 20040216023
    Abstract: A method and system for managing test generation and examination of test coverage so as to most efficiently obtain maximum coverage during test generation. Therefore, in addition to achieving coverage maximization, the present invention also preferably manages test generation in order to increase the efficiency of testing to obtain such coverage maximization. The present invention also preferably provides tactics and/or strategies for generation as part of such management. Thus, coverage providing by test generation and execution is not only measured, but is also preferably obtained in a more efficient manner by enabling the coverage maximization functions to provide feedback and management to the test generation process.
    Type: Application
    Filed: May 24, 2004
    Publication date: October 28, 2004
    Applicant: Verisity Ltd.
    Inventors: Uri Maoz, Amos Noy
  • Patent number: 6684359
    Abstract: A system and method for testing the quality of a simulation model for the DUT (device under test) with dynamic constraint solving and test generation for the testing and verification process. The present invention provides such dynamic constraint solving through the creation of a sequence of instructions in a “generator mini-language” (GML). These instructions are then executed in order to provide a correct random solution to any given set of dynamic constraints. The process of execution is preferably performed by a constraint resolution engine, optionally and more preferably implemented as software, which manages the requirements imposed by the constraints on the execution, while simultaneously enabling a random solution to the set of constraints to be provided. Such a constraint resolution engine may optionally be viewed as a type of state machine, in which individual elements of the state machine are more preferably represented by one or more dynamic graph(s).
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: January 27, 2004
    Assignee: Verisity Ltd.
    Inventor: Amos Noy
  • Patent number: 6519727
    Abstract: A system and method including a simulation model with at least one flexible constraint on a data structure. The term “flexible constraint” indicates that the constraint is not limited to any one type of data structures, but instead can be used for any type of data structure. The preferred data structures include an object, a list of objects and a list of scalars. An object includes at least one data element and optionally a function for operating on the data element. The data element in turn could be a scalar or another object, for example. Preferably, the data structure is not a single scalar The method of the present invention determines the constraint which should be applied to data structure, and then applies the constraint during the test generation process.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: February 11, 2003
    Assignee: Verisity Ltd.
    Inventor: Amos Noy
  • Publication number: 20020166089
    Abstract: A system and method for testing the quality of a simulation model for the DUT (device under test) with dynamic constraint solving and test generation for the testing and verification process. The present invention provides such dynamic constraint solving through the creation of a sequence of instructions in a “generator mini-language” (GML). These instructions are then executed in order to provide a correct random solution to any given set of dynamic constraints. The process of execution is preferably performed by a constraint resolution engine, optionally and more preferably implemented as software, which manages the requirements imposed by the constraints on the execution, while simultaneously enabling a random solution to the set of constraints to be provided. Such a constraint resolution engine may optionally be viewed as a type of state machine, in which individual elements of the state machine are more preferably represented by one or more dynamic graph(s).
    Type: Application
    Filed: March 6, 2001
    Publication date: November 7, 2002
    Inventor: Amos Noy
  • Publication number: 20020040457
    Abstract: A system and method including a simulation model with at least one flexible constraint on a data structure. The term “flexible constraint” indicates that the constraint is not limited to any one type of data structures, but instead can be used for any type of data structure. The preferred data structures include an object, a list of objects and a list of scalars. An object includes at least one data element and optionally a function for operating on the data element. The data element in turn could be a scalar or another object, for example. Preferably, the data structure is not a single scalar The method of the present invention determines the constraint which should be applied to data structure, and then applies the constraint during the test generation process.
    Type: Application
    Filed: April 3, 2001
    Publication date: April 4, 2002
    Inventor: Amos Noy
  • Publication number: 20010010091
    Abstract: Software for test coverage is improved by automatically identifying coverage holes, modifying the input process to test those areas. In a preferred embodiment, the test is rerun iteratively to continue to improve test coverage.
    Type: Application
    Filed: March 6, 2001
    Publication date: July 26, 2001
    Inventor: Amos Noy
  • Patent number: 6219809
    Abstract: The method of the present invention determines constraints which should be applied to data structures, and then applies the constraints during the test generation process. The constraint is applied according to an internal logical order of application. Each constraint of the sequence of constraints is defined. Then a constraint is applied to a data structure for at least reducing the range of possible values, even the possible values are not restricted to one such value. This process is then repeated for other constraints in the sequence. The first constraint in the sequence or at least an earlier constraint in the sequence, is then re-applied, in order to further restrict the range of possible values, and so forth. During this process, preferably the order of suitable application is also determined, such that a constraint which cannot be applied because it requires values which have not yet been defined, is only applied after other constraint(s) which supply the missing values.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 17, 2001
    Assignee: Verisity Ltd.
    Inventor: Amos Noy