Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Abstract: A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.

Abstract: Techniques are described for post-compensation of frequency drift due to changes in crystal oscillator temperature during operation. For example, a clock system is coupled with a crystal oscillator, and can use a reference clock signal from the crystal oscillator to generate an output clock signal using a clock generator. The clock system can monitor an electrical characteristic of a thermal component integrated with the oscillator, which it can map deterministically to a thermal value indicating a temperature of a crystal component of the oscillator. The clock system can then map the temperature deterministically to a frequency shift of the oscillator away from a nominal value. The clock system can then generate a post-compensation signal that directs the clock generator to shift the frequency of the clock output signal so as to compensate for at least a portion of the frequency drift.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.

Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some embodiments, an adjustment block may be employed to adjust the count determined by the learning block based on one or more measured characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.