Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: A user-programmable interconnect device includes a first lower electrode comprising a conductive material. A layer of dielectric material is disposed over the top surface of the lower conductor. An antifuse material, such as one or more layers of a dielectric material, amorphous silicon, or combinations of such materials, is located in an aperture in the dielectric material where the interconnect element of the present invention is to be formed. A second, upper electrode of conductive material is formed over the top of the antifuse material. A portion of the upper electrode located immediately above the antifuse material is fabricated as a fuse material. A passivation layer covers the second electrode and may have an aperture located therein at a location immediately above the antifuse and fuse material. Electrical connections to circuitry incorporating the interconnect element of the present invention are made to the lower and upper electrodes.

Abstract: A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements.

Abstract: A first passive ESD protection device for an electronic component in a microcircuit includes a fuse element shunting the component to be protected and includes a passive programming path from the outside of the microcircuit to the fuse element. A second passive ESD protection device is deactivatable and reactivatable and includes a first fuse element shunted by a second fuse element in series with a first antifuse element. Shunting the second fuse element with a third fuse element in series with a second antifuse element permits a second deactivation and reactivation to be performed. Additional deactivation/reactivation cycles may be permitted by providing additional series combinations of fuse elements and antifuse elements shunting the preceding fuse element. Combinations of the passive protection device and dual elements comprise ESD protection schemes which may be deactivated and activated multiple times.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.